Graphics display system with unified memory architecture
AssigneeBroadcom Corporation
InventorsAlexander G. MacInnis, Chengfuh Jeffrey Tang, Xiaodong Xie, James T. Patterson, Greg A. Kranawetter
Life of this patent
Estimating the term…
Abstract
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
Claims34
A scheduling apparatus capable of providing an interface between a memory and at least a first and second device, the scheduling apparatus comprising:
- a memory request arbiter capable of controlling access to the memory by different devices having different priorities;
- and
- at least one counter coupled to the memory request arbiter, wherein the at least one counter is associated with at least the first device of the at least two devices, and wherein the at least one counter enforces a time-period that precludes access by the first device to the memory.
A scheduling apparatus capable of providing an interface between a memory and at least two devices, the scheduling apparatus comprising:
- a memory request arbiter capable of controlling access to the memory for different devices having different priorities;
- and
- at least one counter coupled to the memory request arbiter, wherein the at least one counter is associated with at least a first device of the at least two devices, and the counter being associated with time-periods, wherein during such time-periods the arbiter prevents the first device from accessing the memory, wherein the scheduling apparatus provides scheduling of tasks, at least one of the tasks not inherently having a pre-determined periodic behavior, and
- wherein the scheduling apparatus is capable of arbitrating access to at least one device that is sensitive to latency.
A scheduling apparatus capable of providing an interface between a memory and at least two devices, the scheduling apparatus comprising:
- a memory request arbiter capable of controlling access to the memory for different devices having different priorities;
- and
- at least one counter coupled to the memory request arbiter, wherein the at least one counter is associated with at least a first device of the at least two devices, and the counter being associated with time-periods, wherein during such time-periods the arbiter prevents higher priority devices from accessing the memory,
- wherein the scheduling apparatus provides scheduling of tasks, at least one of the tasks not inherently having a pre-determined periodic behavior, and
- wherein the scheduling apparatus is capable of arbitrating access to at least one device that is sensitive to latency.
A scheduling apparatus capable of providing an interface between a memory and at least two devices, the scheduling apparatus comprising:
- a memory request arbiter capable of controlling access to the memory for different devices having different priorities;
- and
- at least one counter associated with the memory request arbiter, the counter using time-periods during which at least one of the devices will not have high priority access to the memory.
A scheduling apparatus capable of providing an interface between a memory and at least two devices, the scheduling apparatus comprising:
- a memory request arbiter capable of controlling memory requests for different devices having different priorities;
- and
- at least one counter associated with the memory request arbiter, the counter using time-periods during which at least one of the devices will not make high priority requests to the memory.
Dependencies are inferred from the claim text.