Multiply accumulator for two N bit multipliers and an M bit addend

A multiply accumulator for receiving a first multiplier with N bits, a second multiplier with N bits, and an addend with M bits, M being larger than 2N, the multiply accumulator comprising:

• a modified Booth encoder for receiving a multiplier sign bit, and performing a Booth encoding for a bit inversion of the first multiplier by supplementing the multiplier sign bit behind a least significant bit of the bit inversion of the first multiplier when the multiplier sign bit has a first bit value, and
• a multiplication-and-addition unit for performing a multiplication-and-addition operation of the Booth encoded bit inversion of the first multiplier, the second multiplier, and the addend when the multiplier sign bit has the first bit value, the multiplication-and-addition unit including:
• a carry save adder tree for performing an accumulation of partial products of the Booth encoded bit inversion of the first multiplier and the second multiplier and least significant (2N+1) bits of the addend to generate two carry bits when the multiplier sign bit has the first bit value;
• and
• a sign extension conditional adder for performing operations of:
• adding most significant (M−2N−1) bits of the addend with −1 when both of the two carry bits are 0;
• making the most significant (M−2N−1) bits of the addend unchanged when the two carry bits are 0 and 1, respectively;
• and
• adding the most significant (M−2N−1) bits of the addend with 1 when both of the two carry bits are 1.