Modeling overlapping of memory references in a queueing system model
AssigneeSun Microsystems, Inc.
InventorsIlya Gluhovsky, Brian W. O'Krafka
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Abstract
One embodiment of the present invention provides a system that facilitates modeling the effects of overlapping of memory references in a queueing system model. The system receives a memory reference during execution of a queueing system model. Upon receiving the memory reference, the system determines if the memory reference generates a cache miss. If so, the system models the cache miss in a manner that accounts for possible overlapping of the cache miss with other memory references and other processor operations.
Claims36
A method for modeling the effects of overlapping of memory references in a queueing system model, comprising:
- processing a memory reference during execution of a queueing system model that simulates performance of a memory system;
- determining if the memory reference generates a cache miss;
- and
- if the memory reference generates a cache miss, modeling the cache miss in a manner that accounts for possible overlapping of the cache miss with other memory references and other processor operations.
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for modeling the effects of overlapping of memory references in a queueing system model, the method comprising:
- processing a memory reference during execution of a queueing system model that simulates performance of a memory system;
- determining if the memory reference generates a cache miss;
- and
- if the memory reference generates a cache miss, modeling the cache miss in a manner that accounts for possible overlapping of the cache miss with other memory references and other processor operations.
An apparatus that models the effects of overlapping of memory references in a queueing system model, comprising:
- a processing mechanism configured to process a memory reference during execution of a queueing system model that simulates performance of a memory system;
- and
- a cache simulating mechanism configured to determine if the memory reference generates a cache miss;
- and
- wherein if the memory reference generates a cache miss, the processing mechanism is configured to model the cache miss in a manner that accounts for possible overlapping of the cache miss with other memory references and other processor operations.
Dependencies are inferred from the claim text.