US 2004/0176857 A1 · Multi-processor system

Abstract

A serial communication interface (SCI) cable 4 is provided between the slave processor 2 and the master processor 3. Both processors are connected with a communication interface for peripheral units (SPI: Serial Peripheral Interface) which enables fast transmission. The slave processor 2 transmits a transmission request command which requests at least one of data transmission and reception from the command communication section 220 to the master processor 3 through the SCI cable 4. The master processor 3 transfers data to and from the slave processor 2 in communication with the slave processor 2 by means of the data communication section 310 through the fast SPI cable 5 in response to a transmission request command sent from the slave processor 2 With this, the processing ability of a multi-processor system can be increased.

Claims11

Dependent claims

A multi-processor system comprising:

a slave processor;
a first transmission path connected to said slave processor;
a master processor connected to said first transmission path through which said master processor starts to communicate with said slave processor;
and
a second transmission path which connects said slave processor and said master processor and whose transmission speed is smaller than that of said first transmission path;
wherein
said slave processor is equipped with a command transmission means for sending a transmission request command which requests either data transmission or data reception to said master processor via said second transmission path;
and
said master processor is equipped with a data transmission means for starting data transmission to said slave processor via said first transmission path in response to said transmission request command.

6 more elements

A multi-processor system comprising:

a slave processor (defined as a slave relative to a master processor) having a first single master type bi-directional communication interface unit and a first multi-master type bi-directional communication interface unit whose transmission speed is smaller than that of first single master type bi-directional communication interface;
a master processor (defined as a master to start communication with said slave) having a second single master type bi-directional communication interface unit and a second multi-master type bi-directional communication interface unit whose transmission speed is smaller than that of second single master type bi-directional communication interface unit;
a first transmission cable for connecting said first single master type bi-directional communication interface unit and said second single master type bi-directional communication interface unit;
and
a second communication cable for connecting said first multi-master type bi-directional communication interface unit and said second single multi-master type bi-directional communication interface unit;
wherein
said slave processor is equipped with a first command transmission means for transmitting a transmission request command to ask said master processor to start data transmission from said first multi-master type bi-directional communication interface unit to said master processor via said second communication cable;
and
said master processor causes said second single master type bi-directional communication interface to start communication with said single master bi-directional communication interface unit in response to said transmission request command which was received by said second multi-master type bi-directional communication interface and sends said data to said slave processor via said first communication cable.

6 more elements

Dependencies are inferred from the claim text.

Multi-processor system

Life of this patent

Multi-processor system

Life of this patent

Abstract

Claims11