Semiconductor device having resistor and method of fabricating the same

A method for fabricating a resistor comprising:

• forming a first conductive layer on a semiconductor substrate;
• forming a gate interlayer insulating layer that has two openings exposing predetermined regions of a top surface of the first conductive layer;
• forming a second conductive layer on the semiconductor substrate and the gate interlayer insulating layer;
• patterning the second conductive layer until the gate interlayer insulating layer is exposed, thereby forming second conductive patterns disposed on the two openings;
• forming a mask pattern that connects the second conductive patterns;
• patterning the gate interlayer insulating layer and the first conductive layer using the mask pattern and the second conductive patterns as an etch mask, thereby forming a first conductive pattern and a gate interlayer insulating pattern that are sequentially stacked;
• and
• forming plug interconnections connected to the second conductive patterns.

A method for fabricating a resistor comprising:

• forming a first conductive layer on a semiconductor substrate;
• forming a gate interlayer insulating layer that includes two openings that expose predetermined regions of a top surface of the first conductive layer;
• forming a second conductive layer on the semiconductor substrate and the gate interlayer insulating layer;
• patterning the second conductive layer until the gate interlayer insulating layer is exposed, thereby forming second conductive patterns disposed on the two openings and a dummy pattern spaced apart from the second conductive patterns;
• forming mask patterns covering the gate interlayer insulating layer that is exposed between the second conductive patterns and the dummy pattern;
• using the mask patterns, the second conductive patterns, and the dummy pattern as an etch mask, patterning the gate interlayer insulating layer and the first conductive layer, thereby forming a gate interlayer insulating pattern and a first conductive pattern, respectively, that are sequentially stacked;
• and
• forming plug interconnections connected to the second conductive patterns.

A resistor comprising:

• a first conductive pattern disposed on a predetermined region of a semiconductor substrate;
• second conductive patterns that are disposed on edges of the first conductive pattern and are directly in contact with the first conductive pattern;
• and
• plug interconnections connected to top surfaces of the second conductive patterns.

A semiconductor device comprising:

• a semiconductor substrate including a cell array region and a resistor region;
• a flash memory cell gate pattern disposed at the cell array region, the flash memory cell gate pattern including a floating gate electrode, a cell gate interlayer insulating layer, and a control gate electrode that are sequentially stacked;
• and
• a resistor pattern disposed at the resistor region, the resistor pattern including a first conductive pattern, a gate interlayer insulating pattern, and a second conductive pattern that are sequentially stacked,
• wherein the first conductive pattern, the gate interlayer insulating pattern, and the second conductive pattern are formed of the same materials and have the same thickness as the floating gate electrode, the cell gate interlayer insulating layer, and the control gate electrode, respectively.

A method for fabricating a semiconductor device, comprising:

• preparing a semiconductor substrate including a cell array region and a resistor region;
• forming a flash memory cell gate pattern including a floating gate electrode, a cell gate interlayer insulating layer, and a control gate electrode that are sequentially stacked at the cell array region;
• and
• forming a resistor pattern including a first conductive pattern, a gate interlayer insulating pattern, and a second conductive pattern that are sequentially stacked at the resistor region, wherein the resistor pattern and the flash memory cell gate pattern are simultaneously formed during the same process.