US 2004/0175923 A1 · Semiconductor device and fabrication thereof

Abstract

The object of the present invention is to reduce, in the fabrication of a semiconductor device with a multi-layered interconnection, stresses imposed on conductive elements by interlayer dielectric films made of different materials. For a given multi-layered semiconductor device in which a test conductive element is flanked by plural interlayer dielectric films made of different materials, stresses imposed on the test conductive element by the interlayer dielectric films are determined by calculation. The calculation is based on an equation involving an average thermal expansion coefficient of the dielectric films which is obtained from the thermal expansion coefficients of individual dielectric films and their relative volumes, the temperature at which a conductive material constituting the test conductive element undergoes stress relaxation, and the highest observable temperature during fabrication. Maximum temperature to be observed during fabrication and the materials and relative thicknesses of individual dielectric films are appropriately adjusted such that the stress value obtained by calculation is below a specified tolerable level which is known to cause no void formation around the test conductive element.

Claims14

Dependent claims

A method for fabricating a semiconductor device comprising the steps of:

forming a lower wiring layer on a semiconductor substrate;
coating two or more layers of dielectric films over the lower wiring layer;
forming a via hole and a groove through the dielectric films;
and
forming an upper wiring layer in the groove and a via in the via hole to connect the lower wiring layer with the upper wiring layer,
wherein the maximum process temperature Tprocess—max after forming the dielectric films is determined using following inequality (1):
5 ( α - α diel ′ ) ⁢ E 1 - v ⁢ ( T process_max - T ) ≦ A , ( 1 )
where A represents critical stress value near the via, which is predetermined as a critical value causing voids near the via by a thermal treatment after forming the dielectric films,
α represents a thermal expansion coefficient of the via and the upper wiring layer;
α′diel represents an average thermal expansion coefficient of the dielectric films calculated with their relative thickness;
E represents an elastic coefficient of the via and the upper wiring layer;
ν represents a Poisson's ratio of the via and the upper wiring layer;
and
T represents a stress relaxation temperature of the via and the upper wiring layer.

11 more elements

A method for fabricating a semiconductor device comprising the steps of:

forming a lower wiring layer on a semiconductor substrate;
coating one or more layers of dielectric films over the lower wiring layer;
forming a via hole and a groove through the dielectric films;
and
forming an upper wiring layer in the groove and a via in the via hole to connect the lower wiring layer with the upper wiring layer,
wherein combination of materials of the dielectric films and relative thickness of the dielectric films are determined based on α′diel calculated by following inequality (2):
6 ( α - α diel ′ ) ⁢ E 1 - v ⁢ ( T process_max - T ) ≦ A , ( 2 )
where A represents critical stress value near the via, which is predetermined as a critical value causing voids near the via by thermal treatment after forming the upper wiring layer,
α represents a thermal expansion coefficient of the via and the upper wiring layer;
α′diel represents an average thermal expansion coefficient of the dielectric films calculated with their relative thickness;
E represents an elastic coefficient of the via and the upper wiring layer;
ν represents a Poisson's ratio of the via and the upper wiring layer;
Tprocess—max represents maximum process temperature of the semiconductor device after forming the upper wiring layer;
and
T represents a stress relaxation temperature of the via and the upper wiring layer.

12 more elements

Dependencies are inferred from the claim text.

Semiconductor device and fabrication thereof

Life of this patent

Semiconductor device and fabrication thereof

Life of this patent

Abstract

Claims14