US 2004/0175921 A1Published application

Reduction of the shear stress in copper via's in organic interlayer dielectric material

AssigneeInfineon Technologies North America Corp.

InventorsAndy Cowley, Erdem Kaltalioglu, Mark Hoinkis, Michael Stetter

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Abstract

Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

Claims20

Dependent claims

A method of forming conductors over a semiconductor body having a top surface in which electrical contact areas are formed comprising the steps of:

forming a first inorganic insulating layer having a relatively high k over the top surface;
forming vias completely through the first inorganic insulating layer which are in contact with the contact areas;
filling the vias through the first inorganic insulating layer with conductive material to form conductive plugs which contact the contact areas;
forming a first dielectric insulating layer having a relatively low k over the first inorganic insulating layer;
forming trenches in the first dielectric layer from a top surface thereof;
lining the vias and trenches in the first dielectric insulating layer with a conductive barrier liner layer;
filling the vias and trenches in the first dielectric insulating layer with copper to at least a level of a top surface of the first dielectric insulating layer;
removing a portion of the copper fill in the vias and trenches so as to recess the copper in the vias and trenches from the top surface of the first dielectric insulating layer;
forming a conductive barrier layer on a top surface of the copper in the vias and trenches, said conductive barrier layer having a top surface which is essentially planar with the top surface of the first low k dielectric layer;
forming a second dielectric insulating layer having a relatively low k and being of the same type as the first dielectric insulating layer over the first dielectric insulating layer;
forming vias and trenches in the second dielectric insulating layer and lining same with a conductive barrier liner layer, copper filling, copper recessing, and forming barrier layers over the recessed copper in essentially the same manner as was done with respect to the first dielectric insulating layer;
and
forming a second inorganic layer having a relatively high k over a top surface of the last of the additional plurality of the dielectric insulating layers.

10 more elements

A method of forming conductors over a semiconductor body having a top surface in which electrical contact areas are formed comprising the steps of:

forming a first silicon oxide layer over the top surface of the semiconductor body;
forming vias completely through the first silicon oxide layer which are in contact with the contact areas;
filling the vias through the first silicon oxide layer with conductive material to form conductive plugs which contact the contact areas;
forming a first insulating layer having a lower k than silicon oxide over the first silicon oxide layer;
forming trenches in the first insulating layer from a top surface thereof;
lining the vias and trenches in the first insulating layer with a barrier conductive liner layer;
filling the vias and trenches in the first insulating layer with copper to at least a level of a top surface of the first insulating layer;
removing a portion of the copper fill in the vias and trenches so as to recess the copper in the vias and trenches from the top surface of the first insulating layer;
applying a conductive activation layer over top surfaces of the recessed copper;
forming a conductive barrier layer over the conductive activation layer, said barrier layer having a top surface which is essentially planar with the top surface of the first insulating layer;
forming a second insulating layer of the same type as the first insulating layer over the first insulating layer;
forming vias and trenches in the second insulating layer and lining same with a conductive barrier liner layer, copper filling, copper recessing, and forming barrier layers over the recessed copper in essentially the same manner as was done with respect to the first insulating layer;
and
forming a second silicon oxide layer over a top surface of the second insulating layer.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/379,346Filed 4 Mar 2003
Published: 9 Sep 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10W 20/033
Of conductive barrier, adhesion or liner layers: in openings in dielectrics
H10W 20/037
In openings in dielectrics: the barrier, adhesion or liner layers being on top of a main fill metal
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 20/062
Of conductive parts of the interconnections: by smoothing of conductive parts, e.g. by planarisation