Interface and method of forming an interface for a silicon contact

A method of processing a semiconductor circuit on a substrate covered with an insulating layer, wherein said layer defines an opening over said substrate, and polysilicon contacts a surface of said substrate and a bottom of said opening;

• and wherein said method comprises:
• providing an initial barrier component on at least said polysilicon;
• and
• nitridizing said initial barrier component.

A method of preparing a semiconductor device comprising a container defined by at least one insulation layer, comprising:

• forming a poly plug extending toward said container and having a surface under said container;
• depositing an initial barrier component at least between said poly plug and said container;
• and
• nitridizing a first portion of said initial barrier component, wherein said first portion is next to said container.

A method of forming an interface between a transistor and a capacitor, wherein said transistor includes a doped portion of a substrate, and an in-process poly plug is supported by said doped portion and extends upward along a length to a capacitor site, and wherein said method comprises:

• reducing said poly plug to generally half of said length;
• selectively chemically vapor depositing a barrier component onto said poly plug, wherein said barrier component has a bottom next to said poly plug and a top opposite from said bottom;
• and
• nitridizing said top of said barrier component.

A method of establishing electrical contact between a semiconductor substrate and a semiconductor device, comprising:

• covering said substrate with an insulating layer;
• etching a hole through said insulating layer to said substrate;
• partially plugging said hole with doped polycrystalline silicon;
• depositing at least one metal layer within said hole over said doped polycrystalline silicon;
• nitridizing said at least one metal layer;
• siliciding said at least one metal layer;
• and
• forming said semiconductor device over said at least one metal layer.

A damascene process, comprising:

• forming a first insulation layer over a semiconductor substrate;
• forming a first hole in said first insulation layer;
• forming doped polysilicon in said first hole;
• and
• forming a silicon barrier over said doped polysilicon.

A method of preventing at least some diffusion from a conductive material in a semiconductor device, comprising:

• surrounding a side of said conductive material with an insulator;
• depositing a barrier material onto said conductive material;
• and
• nitridizing said barrier material.

A memory cell, comprising:

• a transistor;
• a capacitor;
• a silicon plug extending from said transistor toward said capacitor and physically separate from said capacitor;
• and
• a diffusion barrier between said silicon plug and said capacitor.

An interface between a poly plug and a storage node of a capacitor, comprising:

• an electrical contact enhancement layer over said poly plug;
• a silicon barrier over said electrical contact enhancement layer;
• and
• an oxidation protection layer over said silicon barrier and contacting said storage node.

A portion of a semiconductor device having an electrically conductive first element, an electrically conductive second element contacting said first element, and an electrically conductive third element configured to electrically communicate with said first element through said second element, wherein said portion comprises:

• an oxidation barrier contacting said third element;
• and
• a silicon diffusion barrier contacting said oxidation barrier and said second element;
• wherein said oxidation barrier and said silicon diffusion barrier are configured to act as an electrical communication interface between said second element and said third element.

An interconnect structure, comprising:

• a doped polysilicon material having a shape defined by an underlying support structure and an adjacent insulative material;
• an electrically conductive material over said doped polysilicon material and said insulative material;
• and
• a silicon barrier between said doped polysilicon material and said electrically conductive material.

An interface for a semiconductor device including a poly plug contacting a substrate and a capacitor plate over said poly plug, comprising:

• a diffusion barrier under said capacitor plate and over said poly plug, said diffusion barrier selected from a group consisting of:
• titanium nitride,
• tungsten nitride,
• rhenium,
• rhenium nitride,
• a platinum-group metal,
• a nitride of said platinum-group metal.
• an oxide of said platinum-group metal,
• an alloy of said platinum-group metal,
• a boride of a transition metal, and
• combinations of the above materials.