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US 2004/0175911 A1Published application
Method for forming MOS transistors with improved sidewall structures
AssigneeTexas Instruments Incorporated
InventorsFreidoon Mehrad, Scott F. Johnson, Reji K. Koshy
Life of this patent
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Abstract
A gate structure (30) is formed over a semiconductor (10). Sidewall structures (200) of a first width W1 are formed adjacent to the gate structure (30) and source and drain regions (90) are formed in the semiconductor (10). An etch process is performed to reduce the width of the sidewall structure to W2 and silicide regions (110) are then formed adjacent to the sidewall structures (205).
Claims11
A method for forming a MOS transistor, comprising:
- providing a semiconductor;
- forming a gate structure over said semiconductor;
- forming sidewall structures of a first width adjacent said gate structure;
- forming source and drain regions in said semiconductor;
- and
- reducing the width of said sidewall structures from said first width to a second width.
3 more elements
A method for forming a MOS transistor, comprising:
- providing a semiconductor;
- forming a gate structure over said semiconductor;
- forming at least one dielectric layer over said gate structure and said semiconductor;
- anisotropically etching said at least one dielectric layer to form sidewall structures of a first width adjacent said gate structure;
- forming source and drain regions in said semiconductor adjacent said sidewall structures;
- and
- reducing the width of said sidewall structures from said first width to a second width.
4 more elements
A method for forming a MOS transistor, comprising:
- providing a semiconductor;
- forming a gate structure over said semiconductor;
- forming a silicon oxide layer over said gate structure and said semiconductor;
- forming a silicon nitride layer over said silicon oxide layer;
- anisotropically etching said silicon oxide layer and said silicon nitride layer to form sidewall structures of a first width adjacent said gate structure;
- forming source and drain regions in said semiconductor adjacent said sidewall structures;
- and
- reducing the width of said sidewall structures from said first width to a second width.
5 more elements
Dependencies are inferred from the claim text.