US 2004/0175888 A1 · Scalable self-aligned dual floating gate memory cell array and methods of forming the array

Abstract

An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate. Other techniques increase the thickness of dielectric between control gates in order to decrease the field coupling between them.

Claims23

Dependent claims

A method of forming a non-volatile memory integrated circuit, comprising:

growing a layer of dielectric across a surface of the substrate,
depositing a layer of conductive material across the dielectric layer,
removing a portion of the Conductive material layer to form a plurality of slots, which leave conductive material layer strips, elongated in a first direction and spaced apart in a second direction, the first and second directions being orthogonal to each other,
thereafter depositing field dielectric over and extending into the plurality of slots between the conductive material layer strips, and
separating the first conductive material layer strips into individual floating gates, thereby forming an array of rows and columns of the floating gates that are individually separated from the substrate surface by the grown layer of dielectric sandwiched therebetween.

2 more elements

A method of forming a non-volatile memory array on a substrate, comprising:

growing a layer of dielectric across a surface of the substrate,
depositing a first layer of polysilicon across the dielectric layer,
removing a portion of the first polysilicon layer to form a first plurality of slots, which leave first polysilicon layer strips, elongated in a first direction and spaced apart in a second direction, the first and second directions being orthogonal to each other,
thereafter depositing field dielectric over and extending into the first plurality of slots between the first polysilicon layer strips,
removing a top portion of the field dielectric to form a uniform surface across the first polysilicon layer strips, thereby leaving field dielectric between the first polysilicon layer strips in the second direction,
thereafter removing a portion of the first polysilicon layer strips and field dielectric in a pattern forming a second plurality of slots continuously elongated in the second direction across a plurality of the first polysilicon layer strips and regularly spaced apart in the first direction, thereby separating the first polysilicon layer strips into segments between the second plurality of slots that have equal lengths in the first direction,
implanting ions into the substrate through the second plurality of slots while the remaining first polysilicon layer strip segments and field oxide act as a mask to block ions from reaching the substrate outside of the second plurality of slots, thereby forming continuous ion strips implanted into the substrate and elongated in the second direction across a plurality of the first polysilicon layer strips,
thereafter forming, from a second layer of polysilicon deposited over said uniform surface and into the second plurality of slots, steering gates elongated in the second direction and spaced apart in the first direction,
separating the individual first polysilicon layer strip segments into two floating gates by removing a portion of the first polysilicon layer strip segments exposed between adjacent steering gates, thereby to form spaces between adjacent floating gates, and
thereafter forming, from a third layer of polysilicon deposited over the steering gates and into the spaces between adjacent floating gates, word lines spaced apart in the second direction and elongated across individual rows of floating gates in the first direction.

7 more elements

A method of forming a non-volatile memory array on a substrate, comprising:

growing a layer of dielectric across a surface of the substrate,
depositing a first layer of polysilicon across the dielectric layer,
removing a portion of the first polysilicon layer to form a first plurality of slots, which leave first polysilicon layer strips, elongated in a first direction and spaced apart in a second direction, the first and second directions being orthogonal to each other,
thereafter depositing field dielectric over and extending into the first plurality of slots between the first polysilicon layer strips,
removing a top portion of the field dielectric to form a uniform surface across the first polysilicon layer strips, thereby leaving field dielectric between the first polysilicon layer strips in the second direction,
thereafter removing a portion of the first polysilicon layer strips and field dielectric in a pattern forming a second plurality of slots continuously elongated in the second direction across a plurality of the first polysilicon layer strips and regularly spaced apart in the first direction, thereby separating the first polysilicon layer strips into individual floating gates,
implanting ions into the substrate through alternate ones of the second plurality of slots, thereby forming continuous ion strips implanted into the substrate and elongated in the second direction across a plurality of rows of floating gates,
thereafter forming polysilicon elements within the individual second plurality of slots at least between adjacent floating gates,
forming, from another layer of polysilicon deposited over said uniform surface and in contact with the polysilicon elements within said alternate ones of the second plurality of slots, steering gates elongated in the second direction and spaced apart in the first direction, and
forming, from a further layer of polysilicon deposited over the steering gates and in contact with the polysilicon elements within others of the second plurality of slots than said alternate ones, word lines spaced apart in the second direction and elongated across individual rows of floating gates in the first direction.

7 more elements

Dependencies are inferred from the claim text.

Scalable self-aligned dual floating gate memory cell array and methods of forming the array

Life of this patent

Scalable self-aligned dual floating gate memory cell array and methods of forming the array

Life of this patent

Abstract

Claims23