Semiconductor device and method for fabricating the same
AssigneeHynix Semiconductor Inc.
InventorSi-Bum Kim
Life of this patent
Estimating the term…
Abstract
A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.
Claims27
A method for forming a semiconductor device, comprising steps of:
- a) forming an insulation layer in a capacitor region and a metal interconnection region on a substrate;
- b) forming a metal interconnection in the metal interconnection region of the insulation layer by performing a dual damascene process;
- and
- c) forming a capacitor in the capacitor region of said insulation layer such that said capacitor is in a same level as the metal interconnection in the insulation layer.
A method for fabricating a semiconductor device, comprising steps of:
- a) forming an insulation layer including a first insulation layer and a second insulation layer in a capacitor region and a metal interconnection region on a substrate formed with a lower conductive layer;
- b) forming an interconnection trench in the metal interconnection region, a first trench in the capacitor region and a via hole connected to the lower conductive layer by selectively etching the insulation layer;
- c) forming a copper interconnection, a first copper interconnection and a via contact plug by forming a first copper layer in the interconnection trench, the via hole and the first trench and planarizing a resulting structure;
- d) forming a second trench by selectively etching the second insulation layer in the capacitor region;
- e) forming a capacitor composed of a first electrode, a dielectric layer and a second electrode on side and bottom surfaces of the second trench;
- and
- f) forming a second copper interconnection by forming a second copper layer on the capacitor and planarizing said second copper layer.
A method for fabricating a semiconductor device, comprising steps of:
- a) forming an insulation layer including a first insulation layer and a second insulation layer in a metal interconnection region and a capacitor region on a substrate formed with a lower conductive layer;
- b) forming an interconnection trench in the metal interconnection region, a first trench in the capacitor region and a via hole by selectively etching the insulation layer;
- c) forming a copper interconnection, a via contact plug and a first copper interconnection by forming a first barrier metal and a first copper layer in the interconnection trench, the via hole and the first trench and planarizing a resulting structure;
- d) forming a second trench by selectively etching the second insulation layer around the first copper interconnection in the capacitor region;
- e) forming a third trench in the first barrier metal by selectively etching the first copper interconnection;
- f) forming a capacitor composed of a first electrode, a dielectric layer and a second electrode on side and bottom surfaces of the second and third trenches;
- and
- g) forming a second copper interconnection by forming a second copper layer on the capacitor and planarizing said second copper layer.
A semiconductor device, comprising:
- a substrate;
- an insulation layer formed in a metal interconnection region and a capacitor region on the substrate;
- a metal interconnection in the insulation layer of the metal interconnection region;
- and
- a capacitor formed in the capacitor region of the insulation layer in a same level as the metal interconnection.
Dependencies are inferred from the claim text.