Static pass transistor logic with transistors with multiple vertical gates

A method for forming a logic gate transistor, comprising:

• forming a source region and a drain region in a horizontal substrate;
• forming a depletion mode channel between the source and the drain regions;
• forming a first vertical gate located above a first portion of the depletion mode channel and separated from the depletion mode channel by a first oxide thickness;
• forming a second vertical gate located above a second portion of the depletion mode channel and separated from the depletion mode channel by a second oxide thickness;
• and
• forming a third vertical gate located above a third portion of the depletion mode channel and separated from the depletion mode channel by the second oxide thickness.

A method for operating a logic circuit, comprising:

• using a number of vertical gates located above a horizontal depletion mode channel between a single source region and a single drain region to provide an applied potential above the depletion mode channel, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, and wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness vertical;
• using at least one of the number of vertical gates as a passing line such that a potential on the passing line does not effect conduction in the depletion mode channel;
• and
• using at least two of the number of vertical gates as a number of active inputs such that the active inputs control conduction in the depletion mode channel.

A method of forming a static pass transistor, comprising;

• forming a source region and a drain region on a horizontal substrate;
• forming a depletion mode channel in the horizontal substrate between the source region and the drain region;
• forming a number of vertical gates above different portions of the depletion mode channel;
• wherein forming a number of vertical gates includes forming at least one of the vertical gates separated from the depletion mode channel by a first oxide thickness (t1);
• and
• wherein forming a number of vertical gates includes forming at least one of the vertical gates separated from the depletion mode channel by a second oxide thickness (t2).

A method for forming a logic gate transistor, comprising:

• forming a source region and a drain region in a horizontal substrate;
• forming a depletion mode channel between the source region and the drain regions;
• forming a first vertical gate located above a first portion of the depletion mode channel and separated from the depletion mode channel by a first oxide thickness;
• forming a second vertical gate located above a second portion of the depletion mode channel and separated from the depletion mode channel by a second oxide thickness;
• and
• forming a third vertical gate located above a third portion of the depletion mode channel and separated from the depletion mode channel by the second oxide thickness.

A method of operating a logic circuit, comprising:

• using a number of vertical gates located above a horizontal depletion mode channel between a single source region and a single drain region to provide an applied potential above the depletion mode channel, wherein at least one of the vertical gates is separated from the depletion mode channel by a first oxide thickness, and wherein at least one of the vertical gates is separated from the depletion mode channel by a second oxide thickness vertical;
• using at least one of the number of vertical gates as a passing line such that a potential on the passing line does not effect conduction in the depletion mode channel;
• and
• using at least two of the number of vertical gates as a number of active inputs such that the active inputs control conduction in the depletion mode channel.