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US 2004/0175859 A1Published application
Single polarity programming of a PCRAM structure
AssigneeMicron Technology, Inc.
InventorsKristy A. Campbell, John T. Moore, Terry L. Gilton
Life of this patent
Estimating the term…
Abstract
A resistance variable memory element with improved data retention and switching characteristics switched between resistance memory states upon the application of write pulses having the same polarity. The resistance variable memory element can be provided having at least one silver-selenide layer in between glass layers, the glass layers are a chalcogenide glass having a GexSe100−x composition.
Claims116
A resistance variable memory element comprising:
- a structure comprising at least one chalcogenide glass layer formed between a pair of electrodes, said layer being constructed and arranged such that a resistance value of said memory element switches from a higher to lower resistance state upon application of a positive voltage in a first voltage range and from a lower to higher resistance state upon application of a positive voltage in a second voltage range.
A resistance variable memory device comprising:
- at least one memory element comprising at least one chalcogenide glass layer;
- and
- a write circuit for applying a first positive voltage to said memory element to switch said memory element from a first resistance state to a second resistance state and for applying a second positive voltage to switch said memory element from said second resistance state to said first resistance state.
A memory element comprising:
- a first electrode;
- a first glass layer comprising GexSe100−x, wherein x=18 to 43, said first glass layer being electrically coupled with said first electrode;
- a first metal containing layer in contact with said first glass layer;
- a second chalcogenide glass layer in contact with said first metal containing layer;
- and
- a second electrode electrically coupled with said second chalcogenide glass layer, said memory element being constructed and arranged such that a resistance value of said memory element switches from a higher to lower resistance state upon application of a positive voltage in a first voltage range and from a lower to higher resistance state upon application of a positive voltage in an second voltage range.
3 more elements
A chalcogenide glass stack comprising:
- a chalcogenide glass layer;
- at least one metal containing layer in contact with said chalcogenide glass layer;
- and
- a second chalcogenide glass layer in contact with said metal containing layer, said chalcogenide glass stack being constructed and arranged such that a resistance value of said memory element switches from a higher to lower resistance state upon application of a positive voltage in a first voltage range and from a lower to higher resistance state upon application of a positive voltage in an second voltage range different from said first voltage range.
1 more element
A memory element comprising:
- a first electrode;
- at least one first chalcogenide glass layer in electrical communication with said first electrode;
- at least one first metal containing layer in contact with said at least one first chalcogenide glass layer;
- at least one second chalcogenide glass layer in contact with said at least one first metal containing layer;
- at least one second metal containing layer in contact with said at least one second chalcogenide glass layer;
- at least one third chalcogenide glass layer in contact with said at least one second metal containing layer;
- and
- a second electrode in electrical communication with said at least one third chalcogenide glass layer, said memory element being constructed and arranged such that a resistance value of said memory element switches from a higher to lower resistance state upon application of a positive voltage in a first voltage range and from a lower to higher resistance state upon application of a positive voltage in an second voltage range, said second voltage range being different from the first voltage range.
5 more elements
A method of forming a resistance variable memory element comprising the steps of:
- forming a first electrode;
- forming a first chalcogenide glass layer in contact with said first electrode;
- forming a first metal containing layer in contact with said first chalcogenide glass layer;
- and
- forming a second chalcogenide glass layer in electrical communication with said first metal containing layer;
- forming a second metal containing layer in contact with said first chalcogenide glass layer;
- forming a third chalcogenide glass layer in contact with said second metal containing layer;
- and
- forming a second electrode in electrical communication with said third chalcogenide glass layer, said memory element being constructed and arranged such that a resistance value of said memory element switches from a higher to lower resistance state upon application of a positive voltage in a first voltage range and from a lower to higher resistance state upon application of a positive voltage in an second voltage range.
6 more elements
A method of forming a resistance variable memory element comprising:
- forming a first chalcogenide glass layer;
- forming a silver-selenide layer in contact with said first glass layer;
- and
- forming a second chalcogenide glass layer in contact with said silver-selenide layer, said memory element being constructed and arranged such that a resistance value of said memory element switches from a higher to lower resistance state upon application of a first positive voltage and from a lower to higher resistance state upon application of a positive voltage in an second voltage.
1 more element
A processor-based system, comprising:
- a processor;
- and
- a memory circuit connected to said processor, said memory circuit including a resistance variable memory element comprising at least one metal containing layer, at least one chalcogenide glass layer, at least one other chalcogenide glass layer, said metal containing layer being provided between said at least one chalcogenide glass layer and said at least one other chalcogenide glass layer, said memory element being constructed and arranged such that a resistance value of said memory element switches from a higher to lower resistance state upon application of a first positive voltage and from a lower to higher resistance state upon application of a second positive voltage.
A processor-based system, comprising:
- a processor;
- a memory circuit connected to said processor, said memory circuit comprising a first electrode;
- at least one first chalcogenide glass layer in electrical communication with said first electrode;
- at least one first metal containing layer in contact with said at least one first chalcogenide glass layer;
- at least one second chalcogenide glass layer in contact with said at least one first metal containing layer;
- at least one second metal containing layer in contact with said at least one second chalcogenide glass layer;
- at least one third chalcogenide glass layer in contact with said at least one second metal containing layer;
- and
- a second electrode in electrical communication with said at least one third chalcogenide glass layer, said memory circuit being constructed and arranged such that a resistance value of said memory circuit switches from a higher to lower resistance state upon application of a first positive voltage and from a lower to higher resistance state upon application of a second positive voltage.
6 more elements
A memory element comprising:
- a first electrode;
- a second electrode;
- and
- a plurality of chalcogenide glass layers and at least one metal containing layers arranged between said first and second electrodes, whereby said plurality of chalcogenide glass layers alternate with said at least one metal containing layers, with one of said chalcogenide glass layers being in contact with said first electrode and another of said chalcogenide glass layers being in contact with said second electrode, said memory element being constructed and arranged such that a resistance value of said memory element switches from a higher to lower resistance state upon application of a positive voltage in a first voltage range and from a lower to higher resistance state upon application of a positive voltage in an second voltage range.
1 more element
A method of forming a resistance variable memory element comprising:
- forming a first electrode;
- forming a second electrode;
- and
- forming a plurality of chalcogenide glass layers and at least one metal containing layer between said first and second electrodes, whereby said plurality of chalcogenide glass layers alternate with said at least one metal containing layers, with one of said chalcogenide glass layers being in contact with said first electrode and another of said chalcogenide glass layers being in contact with said second electrode, said layers being constructed and arranged such that a resistance value of said memory element switches from a higher to lower resistance state upon application of first a positive voltage and from a lower to higher resistance state upon application of a second positive voltage.
1 more element
A resistance variable memory element comprising a PCRAM stack including amorphous semiconducting glass layers separated by a layer of silver-containing material, wherein the resistance variable memory element switches to a low resistance state upon application of a first positive write pulse, and switches to a high resistance state by application of a second positive write pulse.
A resistance variable memory element comprising a PCRAM stack including amorphous semiconducting glass layers separated by a layer of silver-containing material, wherein a resistance value of the resistance variable memory element is switchable between two discrete states, one lower and the other high, upon application of respective positive voltages.
Dependencies are inferred from the claim text.