Test system and manufacturing of semiconductor device
AssigneeRenesas Technology Corp.
InventorsIsao Shimizu, Masayuki Sato, Hiroshi Fukiage
Life of this patent
Estimating the term…
Abstract
A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.
Claims24
A test system which performs electrical tests on semiconductor chips formed on a semiconductor wafer, comprising:
- a probe card which is provided with conductive needles in alignment with the placement of electrode pads in the semiconductor chips and connected to a test circuit;
- a test circuit which is placed on said probe card and conducts tests on the semiconductor chips, based on a program;
- and
- a control device which writes a program in said test circuit and stores therein a test result outputted from said test circuit.
A test system which conducts electrical tests on semiconductor chips formed on a semiconductor wafer, comprising:
- a test circuit which conducts tests on the semiconductor chips formed in arbitrary positions of the semiconductor wafer;
- a probing module having test wirings formed therein, which connect the semiconductor chips and said test circuit;
- and
- a power supply device which supplies power to said each semiconductor chip and said test circuit through said probing module.
A test system which performs electrical tests on semiconductor chips formed on a semiconductor wafer, comprising:
- a test circuit which is formed in a scribe area or a chip area in the semiconductor wafer and tests the semiconductor chips;
- and
- test wirings which are formed in the scribe area or a test wiring layer in the semiconductor wafer and connect said test circuit to the semiconductor chips.
A method of generating a test program, comprising the following steps of:
- describing functions set every blocks in a tester for conducting electrical tests on semiconductor chips formed on a semiconductor wafer and a function of said each semiconductor chip to be tested, in hardware description language;
- inputting said hardware description and a test program to a hardware emulator;
- performing simulation by the hardware emulator;
- and
- debugging the test program.
A method of manufacturing a semiconductor integrated circuit device, comprising the following steps of:
- forming a plurality of semiconductor chips each having a desired function on a semiconductor wafer;
- placing a test circuit connected to needles and operated in accordance with a program to test said each semiconductor chip, on a probe substrate having a size corresponding to the semiconductor wafer and having the conductive needles formed thereon in alignment with the placement of electrode pads on the semiconductor chips;
- superimposing the probe substrate on the semiconductor wafer in such a manner that the needles are brought into contact with the corresponding electrode pads of the semiconductor chips;
- testing said each semiconductor chip by the test circuit;
- and
- selecting a semiconductor chip judged to be non-defective, as a product according to the test.
A method of manufacturing a semiconductor integrated circuit device, comprising the following steps of:
- forming a test circuit module which is operated in accordance with a program and tests each of a plurality of semiconductor chips, on a semiconductor wafer on which said plurality of semiconductor chips are formed;
- supplying a source voltage to at least said test circuit module from the outside to thereby test said each semiconductor chip on the semiconductor wafer by said test circuit module;
- and
- selecting the semiconductor chip judged to be non-defective by said test, as a product.
Dependencies are inferred from the claim text.