Closed loop sub-carrier synchronization system

A method for synchronizing sampled signals, the method comprising:

• receiving a current sampled signal;
• retrieving a stored sampled signal from a memory;
• generating a coarse synchronization signal;
• outputting the current sampled signal;
• outputting the stored sampled signal in response to the coarse synchronization signal;
• determining a phase difference between the output current sampled signal and the output stored sampled signal;
• determining a phase adjustment based on the phase difference between the output current sampled signal and the output stored sampled signal;
• and
• adjusting the phase of at least one of the output current sampled signal and the output stored sampled signal according to the determined phase adjustment.

A system for synchronizing a first sampled signal and a second sampled signal, the system comprising:

• a first logic circuit that receives a first sampled signal and generates a synchronization signal based on at least one of the first sampled signal and a sampled signal preceding the first sampled signal;
• a second logic circuit that retrieves a stored sampled signal from memory and generates a second sampled signal based on the stored sampled signal;
• and
• a third logic circuit coupled to the first and second logic circuits that receives the synchronization signal from the first logic circuit and the second sampled signal from the second logic circuit and outputs the second sampled signal synchronized to the first sampled signal in response to the synchronization signal.

A system for synchronizing a first sampled signal and a second sampled signal, the system comprising:

• a first logic circuit that comprises a memory;
• a second logic circuit that receives the first sampled signal and generates a cropped sampled signal by removing samples from the first sampled signal;
• a third logic circuit coupled to the first and second logic circuits that receives the cropped sampled signal from the second logic circuit and stores the cropped sampled signal in the first logic circuit;
• a fourth logic circuit coupled to the first logic circuit that retrieves the cropped sampled signal stored in the first logic circuit and generates a restored sampled signal by adding samples to the retrieved cropped sampled signal;
• a fifth logic circuit coupled to the fourth logic circuit that receives the restored sampled signal from the fourth logic circuit and outputs the restored sampled signal synchronized with the second sampled signal.

A method for synchronizing sampled signals, the method comprising:

• receiving a first sampled signal;
• storing a stored sampled signal in memory, the stored sampled signal comprising at least one of the first sampled signal and a signal derived from the first sampled signal;
• receiving a second sampled signal;
• reading the stored sampled signal from memory;
• outputting the second sampled signal;
• and
• outputting an output sampled signal synchronized to the second sampled signal, the output sampled signal being based on the stored sampled signal read from memory.

A system for synchronizing a first sampled signal and a second sampled signal, the system comprising:

• a first logic circuit that receives a first sampled signal and a second sampled signal;
• a memory circuit;
• a second logic circuit communicatively coupled to the first logic circuit and the memory circuit that stores a stored sampled signal in the memory circuit, the stored sampled signal comprising at least one of the first sampled signal and a signal derived from the first sampled signal;
• a third logic circuit communicatively coupled to the memory circuit that reads the stored sampled signal from the memory circuit;
• a fourth logic circuit communicatively coupled to the first logic circuit that outputs the second sampled signal;
• and
• a fifth logic circuit communicatively coupled to the third logic circuit and the fourth logic circuit that outputs an output sampled signal synchronized to the second sampled signal, the output sampled signal being based on the stored sampled signal read from the memory circuit.