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US 2004/0174906 A1Published application
Packet processing circuit
AssigneeNEC Corporation
InventorTakahiro Ohkuma
Life of this patent
Estimating the term…
Abstract
A packet processing circuit includes a plurality of macros and a clock supply unit. Each of the macros processes packet data on the basis of a clock and outputs the processed packet data from at least one route. The macros are cascade-connected. The clock supply unit supplies the clock to a macro to be controlled and, when no packet data is output for a predetermined time from all routes of a macro on the input side of the macro to be controlled, stops supplying the clock to the macro to be controlled.
Claims7
A packet processing circuit comprising:
- a plurality of macros each of which processes packet data on the basis of a clock and outputs the processed packet data from at least one route, said macros being cascade-connected;
- and
- a clock supply unit which supplies the clock to a macro to be controlled and, when no packet data is output for a predetermined time from all routes of a macro on an input side of said macro to be controlled, stops supplying the clock to said macro to be controlled.
Dependencies are inferred from the claim text.