Lossless, stateful, real-time pattern matching with deterministic memory resources
AssigneeForte 10 Networks, Inc.
InventorLivio Ricciulli
Life of this patent
Estimating the term…
Abstract
A method and apparatus for inspecting packets is disclosed. In one embodiment, the method comprises broadcasting data units of packets to a plurality of finite state machine (FSM) comparison units, where each of the FSM comparison units implements a portion of a signature. The method further includes comparing the data units of the packets to signatures, including each FSM comparison unit of the plurality of FSM comparison units independently comparing one of the data units to its associated portion of one signature. The method also includes combining results of the plurality of FSM comparison units independently processing the data units using a logic combinatorial circuit.
Claims25
A method comprising:
- broadcasting data units of packets to a plurality of finite state machine (FSM) comparison units, each of the FSM comparison units implementing a portion of a signature;
- comparing the data units of the packets to a plurality of signatures, including each FSM comparison unit of the plurality of FSM comparison units independently comparing one of the data units to its associated portion of one signature;
- and
- combining results of the plurality of FSM comparison units independently processing the data units using a logic combinatorial circuit.
An apparatus comprising:
- a plurality of finite state machine (FSM) comparison units to compare data units of the packets to a plurality of signatures, each of the FSM comparison units implementing a portion of a signature, wherein each FSM comparison unit of the plurality of FSM comparison units independently compares one of the data units to its associated portion of one signature;
- and
- a logic combinatorial circuit to combine results of the plurality of FSM comparison units independently processing the data units.
An apparatus comprising:
- means for broadcasting data units of packets to a plurality of finite state machine (FSM) comparison units, each of the FSM comparison units implementing a portion of a signature;
- means for comparing the data units of the packets to a plurality of signatures, including each FSM comparison unit of the plurality of FSM comparison units independently comparing one of the data units to its associated portion of one signature;
- and
- means for combining results of the plurality of FSM comparison units independently processing the data units using a logic combinatorial circuit.
Dependencies are inferred from the claim text.