Method and system for dynamically increasing output rate and reducing length of a delay chain

A method of processing samples of a data packet comprising:

• reading the samples from a data packet into a tapped delay chain comprising a plurality of pipelined registers;
• processing samples from taps on the delay chain to synchronize a data packet;
• subsequent to synchronization of the data packet, shifting samples rapidly from the delay chain at a higher rate than samples coming in;
• reducing the length of the delay chain by bypassing empty registers;
• and
• repeating the steps of shifting samples rapidly and reducing the length of the delay chain.

An apparatus comprising:

• a pipeline of registers that store data samples;
• logic circuitry which controls the output of each individual register from the pipeline of registers;
• a multiplexer having inputs from select registers from the pipeline of registers, and an output;
• and
• a processor which controls the data shifting rates, the logic circuitry, and the output of the multiplexer.

An apparatus comprising:

• a pipeline of registers that stores data samples of a data packet;
• a timing recovery module for synchronization of the data packet that initiates a transition;
• a logic circuitry which controls the output of each individual register from the pipeline of registers;
• a multiplexer having inputs from select registers from the pipeline of registers, and an output;
• and
• a processor having inputs from a timing recovery module for packet synchronization which controls the data shifting rates, the logic circuitry, and the output of the multiplexer.

An apparatus comprising:

• means for reading data samples into a tapped delay chain;
• means for processing data samples from taps on the delay chain;
• means for shifting data samples rapidly from the delay chain at a higher rate than data samples coming in;
• and
• means for reducing the length of the delay chain.