Programmable address generator
AssigneeSTMicroelectronics S.r.l.
InventorPhilippe Dreux
Life of this patent
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Abstract
A programmable address generator comprising at least one input for receiving a first digital address of a data word in a first memory, to be converted into a second digital address of this same data word in a second memory, or conversely, comprising: at least two hierarchically interleaved counters, that can be individually parameterized for their initial offset, their increment value, and their maximum count; at least one programming register containing said parameters of each counter, these parameters depending on the addressing conversion function to be performed; and an adder of the first address with the counter results, said adder providing said second address.
Claims21
A programmable address generator comprising at least one input for receiving a first digital address of a data word in a first memory, to be converted into a second digital address of this same data word in a second memory, or conversely, comprising:
- at least two hierarchically interleaved counters, that can be individually parameterized for their initial offset, their increment value, and their maximum count;
- at least one programming register containing said parameters of each counter, these parameters depending on the addressing conversion function to be performed;
- and
- an adder of the first address with the counter results, said adder providing said second address.
An address generator, comprising:
- a first counter operable to receive a first clock, to generate a first count in response to the first clock, and to generate a second clock in response to the first count;
- a second counter coupled to the first counter and operable to generate a second count in response to the second clock;
- and
- an adder coupled to the first and second counters and operable to generate an address by combining the first and second counts.
A computer system, comprising:
- an address bus;
- and
- an address generator coupled to the address bus and comprising,
- a first counter operable to receive a first clock, to generate a first count in response to the first clock, and to generate a second clock in response to the first count,
- a second counter coupled to the first counter and operable to generate a second count in response to the second clock, and
- an adder coupled to the first and second counters and operable to generate an address by combining the first and second counts.
A method, comprising:
- generating a first count in response to a first clock;
- generating a second clock in response to the first count;
- generating a second count in response to the second clock;
- and
- generating an address by combining the first and second counts.
Dependencies are inferred from the claim text.