Double data rate synchronous dynamic random access memory semiconductor device

A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device comprising:

• a delay locked loop (“DLL”) circuit, which compensates for skew of an input clock signal and generates an output clock signal;
• a clock signal control unit, which receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active;
• an output unit, which buffers data stored in the DDR SDRAM semiconductor device and outputs the data to the outside of the DDR SDRAM semiconductor device, in synchronization with the output clock signal output from the clock signal control unit;
• and
• an output control unit, which receives the output clock signal, output from the clock signal control unit, and the read signal, and outputs the read signal to the output unit in synchronization with the output clock signal output from the clock signal control unit.

A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device comprising:

• a delay locked loop (“DLL”) circuit, which compensates for skew of an input clock signal and generates an output clock signal;
• a first logic unit, which receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, and a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and activates its output signal when either the read signal or the DLL locking signal is active;
• a second logic unit, which receives the output signal of the first logic unit and the output clock signal of the DLL circuit, and outputs the output clock signal when the output signal of the first logic unit is active;
• an output unit, which buffers and outputs data stored in the DDR SDRAM semiconductor device, in synchronization with the output clock signal of the second logic unit;
• and
• an output control unit, which receives the output clock signal of the second logic unit and the read signal, and outputs the read signal to the output unit in synchronization with the output clock signal of the second logic unit.

A semiconductor memory device comprising:

• a delay locked loop (“DLL”) circuit for receiving an input clock signal and generating a deskewed output clock signal;
• an output unit for buffering data stored within the semiconductor memory device and outputting the data;
• and
• an output control unit in signal communication with the DLL circuit and the output unit for deactivating the output unit when the DLL circuit performs a locking operation on the input clock signal.