Content addressable memory with redundant repair function

A content addressable memory for making a comparison between input information and retrieval information, comprising:

• a memory array including a plurality of memory cell rows storing said retrieval information, and a plurality of redundant memory cell rows repairing a faulty memory cell row,
• said plurality of memory cell rows being divided into a plurality of memory cell row groups, each group including a predetermined number of the memory cell rows, corresponding to a part of bits of addresses of said plurality of memory cell rows;
• a first shift circuit shifting, if necessary, each of at least one memory cell row group to be accessed in a first direction during data reading and data writing;
• a second shift circuit shifting each of said at least one memory cell row group shifted in said first direction by said first shift circuit in a second direction opposite to said first direction in data retrieving;
• an address producing circuit producing an intended address based on information transmitted from each of said memory cell row group through said second shift circuit in said data retrieving;
• a plurality of stages of latch circuits provided corresponding to respective addresses of said plurality of memory cell row groups, and each latching a shift signal instructing an operation of shifting the corresponding memory cell row group in said first and second shift circuits;
• and
• a shift signal producing portion producing said shift signal to be latched by each of said latch circuits based on a faulty address of said faulty memory cell row.

A content addressable memory for making a comparison between input information and retrieval information, comprising:

• a memory array including a plurality of memory cell rows storing said retrieval information, and a redundant memory cell row repairing a faulty memory cell row;
• a first shift circuit shifting, if necessary, each of at least one memory cell row to be accessed in a first direction during data reading and data writing;
• a second shift circuit shifting each of said at least one of memory cell row shifted in said first direction by said first shift circuit in a second direction opposite to said first direction in data retrieving;
• an address producing circuit producing an intended address based on information transmitted from each of said memory cell rows through said second shift circuit in said data retrieving;
• and
• a control circuit controlling said first and second shift circuits based on a faulty address of said faulty memory cell row, wherein
• said memory array further includes match lines provided corresponding to said memory cell rows including the redundant memory cell row, respectively, and determining whether said input information matches with a portion of said retrieval information stored in said respective memory cell rows,
• each of said memory cell rows including said redundant memory cell row has a plurality of memory cells each storing one bit of storage data, and
• each of said memory cells includes:
• a first cell unit having a first storage node holding first data,
• a second cell unit having a second storage node holding second data, and
• a comparing circuit comparing a pair of data held on said first and second storage nodes with input data forming said applied input information, and selectively driving the corresponding match line in accordance with a result of the comparison.