Integrated circuit memory device including delay locked loop circuit and delay locked loop control circuit and method of controlling delay locked loop circuit

A method of controlling a delay lock loop (DLL) circuit of an integrated circuit memory device, comprising:

• controlling a DLL power supply to selectively supply power to the DLL circuit during a refresh mode of the integrated circuit memory device.

An integrated circuit memory device, comprising:

• a delay locked loop (DLL) circuit receives an external clock signal and generates an internal clock signal;
• wherein the DLL circuit is turned on during a first refresh operation and is turned off during a second refresh operation.

An integrated circuit memory device, comprising:

• a delay locked loop (DLL) circuit, the DLL circuit generates a first clock signal based on a reference clock signal and locking information, the locking information being information on a phase relationship between the first clock signal and the reference clock signal;
• and
• a control signal generator controlling the DLL circuit to selectively reset the locking information during a refresh mode of the integrated circuit memory device based on a selection signal.