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AssigneeIndian Institute of Science
InventorsNavakanta Bhat, Mukherjee Sugato
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A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is proposed. The system is novel because it recognizes that no matter what, the transistor mismatch is statistical in nature and hence it is prudent to exploit the nature of the distribution to get fast and slow circuits rather than make all circuits slow to meet 6σ design index. The system comprises of sense amplifier, multiplexer, delay elements, and provision for hardwiring fast and slow circuits during packaging. The sense amplifier firing path is split into slow and fast path and the multiplexer can select one of these. The memory circuits are tested after fabrication to assess whether they could be partitioned as slow or fast circuits and accordingly an appropriate path is selected by the multiplexer. This path is then hardwired during packaging by connecting the select input of multiplexer to VDD or GND.
A system for high yield and speed enhancement of semiconductor integrated circuits such as SRAM and DRAM using post fabrication transistor mismatch compensation circuitry consisting of sense amplifier, multiplexer, delay elements and hardwiring arrangement during packaging, comprising a novel sense amplifier instrument for providing high memory yield and speed enhancement using post fabrication, transistor mismatch compensation circuit, wherein sense amplifier firing path being split into two paths, one path corresponding to fast chips and the other to the slow chips, means for effecting delay in the fast and slow paths and multiplexer which selects one of the two parts to fire the sense amplifier such that more than 80% of the memory integrated circuits (fast path) are very fast and the rest of the memory integrated circuits (slow path) are still functional without compromising the yield.
A system for high yield and speed enhancement of semiconductor integrated circuits using post fabrication transistor mismatch compensation technique as described in the Complete specification and as illustrated by way of drawings.
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