Memory device with high charging voltage bit line
AssigneeWindbond Electronics Corp.
InventorChieng-Chung Chen
Life of this patent
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Abstract
A memory device with high charging voltage bit lines, comprising: memory cells, sense amplifiers, and high charging voltage bit line circuits. Herein, the memory cell is used to store data and electrically couples with a pair of bit lines. The sense amplifier with a pair of sense nods, which electrically couples with the pair of bit lines, is used to sense the differential voltage levels of the pair of sense nodes while the memory cell is active. The high charging voltage bit line circuit is used to provide a charging voltage, which is higher than the logical high voltage of the memory cell, for charging the memory cell.
Claims19
A memory device with high charging voltage bit lines, said memory device comprising:
- a plurality of memory cells storing data and being electrically coupled with a plurality of bit line pairs;
- a plurality of sense amplifiers with a plurality of sense node pairs, wherein said plurality of sense node pairs are electrically coupled with said plurality of bit line pairs, and said plurality of sense amplifiers sense the differential voltage of said plurality of sense node pairs while said plurality of memory cells are active;
- and
- a plurality of high charging voltage bit line circuits having a plurality of voltage charging circuits for providing a charging voltage, wherein said charging voltage is higher than the logical high voltage level of said plurality of memory cells to charge said plurality of memory cells.
A memory device with high charging voltage bit lines, said memory device comprising:
- a plurality of memory cells storing data and being electrically coupled with a plurality of bit line pairs;
- a plurality of sense amplifiers with a plurality of sense node pairs, wherein said plurality of sense node pairs are electrically coupled with said plurality of bit line pairs, and said plurality of sense amplifiers sense the differential voltage of said plurality of sense node pairs while said plurality of memory cells are active;
- and
- a plurality of high charging voltage bit line circuits, comprising:
- a plurality of voltage charging circuits for providing a charging voltage, wherein said charging voltage is higher than the logical high voltage level of said plurality of memory cells to charge said plurality of memory cells.
A method of charging memory cells, wherein using a voltage, which is higher than the logical high voltage level of memory, to charge memory cells, comprising:
- enabling said plurality of memory cells, wherein said plurality of memory cells are electrically coupled with a plurality of bit line pairs;
- sensing and amplifying the differential voltage of a plurality of sense node pairs while said plurality of memory cells are active;
- and
- providing a high charging voltage for charging said plurality of memory cells, wherein said high charging voltage is higher than the logical high voltage level of said plurality of memory cells.
Dependencies are inferred from the claim text.