Output buffer register, electronic circuit and method for delivering signals using same

A method for delivering output signals with the aid of an output buffer register, the method comprises the steps:

• applying a given number N of input signals to the data inputs of N respective flip-flops of a first flip-flop register comprising a given number N of flip-flops each having a data input, a data output, and an enable input;
• linking the data outputs of the N flip-flops of the first flip-flop register, respectively, to N first inputs of an output multiplexer having N first inputs, N second inputs, N outputs, and a selection input;
• linking the data inputs of N flip-flops of a second flip-flop register comprising N flip-flops each having a data input, a data output, and an enable input, respectively, to the N outputs of the output multiplexer which deliver N respective output signals;
• linking the N data outputs of the N flip-flops of the second register, respectively, to the N second inputs of the output multiplexer;
• linking the data output of a third flip-flop register comprising a flip-flop having a data input, a data output and an enable input, to the selection input of the output multiplexer;
• applying an enable signal to the data input;
• and
• applying one and the same clock signal to the enable inputs of the flip-flops of the first, second and third registers.

An electronic system comprising:

• a system bus;
• and
• at least one system module connected to the system bus by way of an appropriate communication port, wherein the system module comprises an output buffer register arranged upstream of the communication port, the output buffer register comprising:
• a first flip-flop register comprising a given number N of flip-flops each having a data input, a data output, and an enable input;
• a second flip-flop register comprising N flip-flops, each having a data input, a data output, and an enable input;
• a third flip-flop register comprising a flip-flop having a data input, a data output, and an enable input;
• and
• an output multiplexer having N first inputs, N second inputs, N outputs and a selection input, and wherein
• the enable inputs of the flip-flops of the first, second, and third registers, receive one and the same clock signal;
• the data inputs of the N flip-flops of the first register respectively receive N input signals;
• the data outputs of the N flip-flops of the first register are respectively linked to the the N first inputs of the output multiplexer;
• the N outputs of the output multiplexer deliver N respective output signals;
• the data inputs of the N flip-flops of the second register are respectively linked to the N outputs of the output multiplexer;
• the N data outputs of the N flip-flops of the second register are respectively linked to the N second inputs of the output multiplexer;
• the data input of the third register receives an enable signal;
• and
• the data output of the third register is linked to the selection input of the output multiplexer.

An integrated circuit comprising:

• a circuit supporting substrate;
• and
• at least one output buffer at least partly disposed on the circuit supporting substrate, wherein the at least one output buffer comprises:
• an output buffer register arranged upstream of the communication port, the output buffer register comprising:
• a first flip-flop register comprising a given number N of flip-flops each having a data input, a data output, and an enable input;
• a second flip-flop register comprising N flip-flops, each having a data input, a data output, and an enable input;
• a third flip-flop register comprising a flip-flop having a data input, a data output, and an enable input;
• and
• an output multiplexer having N first inputs, N second inputs, N outputs and a selection input, and wherein
• the enable inputs of the flip-flops of the first, second, and third registers, receive one and the same clock signal;
• the data inputs of the N flip-flops of the first register respectively receive N input signals;
• the data outputs of the N flip-flops of the first register are respectively linked to the the N first inputs of the output multiplexer;
• the N outputs of the output multiplexer deliver N respective output signals;
• the data inputs of the N flip-flops of the second register are respectively linked to the N outputs of the output multiplexer;
• the N data outputs of the N flip-flops of the second register are respectively linked to the N second inputs of the output multiplexer;
• the data input of the third register receives an enable signal;
• and
• the data output of the third register is linked to the selection input of the output multiplexer.