Programmable reference for 1T/1C ferroelectric memories

A ferroelecteric memory, comprising:

• an array of ferroelectric memory cells organized in a 1T1C type architecture having a plurality of bit line pairs;
• a sense amplifier circuit selectively coupled across the pair of bit lines, and operable to generate an output state based on a voltage difference between the pair of bit lines;
• and
• a logic programmable capacitance reference circuit selectively coupled to one of the pair of bit lines, and operable to generate a reference voltage during a sense mode of operation, wherein a value of the reference voltage is variable and a function of one or more memory conditions.

A 1T1C ferroelectric memory device, comprising:

• a plurality of bit lines pairs, having ferroelectric memory cells selectively coupled thereto;
• a sense amplifier circuit coupled across a bit line pair, and operable to generate an output state indicative of a voltage difference across the bit line pair associated therewith;
• a logic programmable capacitance reference circuit operable to generate a reference voltage having a value that is a function of one or more memory conditions, the logic programmable capacitance reference circuit further comprising:
• a variable capacitance reference circuit comprising a plurality of ferroelectric capacitors selectively coupled together in parallel via a plurality of control switches, respectively, wherein a state of the control switches is dictated by the one or more memory conditions, thereby defining a capacitance value that is a function of the one or more memory conditions,
• wherein the plurality of bit line pairs collectively form a memory block, and wherein the capacitance of the variable capacitance reference circuit couples to one of the bit lines in each of the plurality of bit line pairs, and forms a capacitive divider therewith, thereby defining the reference voltage that serves as a shared reference voltage for each of the bit line pairs.