Non-volatile semiconductor memory device and memory system using the same

A memory system, comprising:

• a control circuit having a data register for storing write data, said control circuit controlling operation of the memory system;
• and
• a plurality of memory means each having a plurality of memory cells, each for executing data write operation for latching a data group composed of data of predetermined bits transferred from the data register and for writing the latched data group in the memory cells, and executing write verify operation for checking whether all the data of the data group have been written correctly and for outputting a collective verify signal when all the data of the data group have been written completely;
• wherein whenever said control circuit receives the collective verify signal outputted from one of said memory means, said control circuit executes a data transfer operation for transferring a new data group to one of said memory means and for allowing one of said memory means to latch the new data group, and said one of said memory means writes the latched new data group therein, whenever said one of said memory means executes the write operation for allowing one of said memory means to write new latched data group therein completely, said one of memory means transferring the collective verify signal to said control circuit, said control circuit executing another data transfer operation for transferring another new data group to another of said memory means during the one of memory means executes the write and verify operation, the data write operation to one of said memory means and the data transfer operation to another of said memory means being executed simultaneously in parallel to each other and repeatedly.

A cache memory system, comprising:

• a main memory, a cache memory, and a control circuit for controlling data transfer operation between said main memory and said cache memory, and
• wherein said main memory is comprised of a plurality of erase blocks each having memory cells predetermined bits, and outputs an erase verify signal whenever all bits of one of the erase blocks have been erased;
• and
• wherein when accessed data are not present in said cache memory at cache mishit, said control circuit erases data of one of said erase blocks;
• and after the data have been erased completely and thereby the erase verify signal has been outputted, said control circuit executes data rewrite operation for rewriting data in said cache memory into the erased erase block.