Nonvolatile semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorTomoharu Tanaka
Life of this patent
Estimating the term…
Abstract
A bit line is connected to a data circuit for use in a program/read time. The data circuit includes first, second, and third data storage units. The first data storage unit is connected to the bit line. A first data transfer circuit is connected between the first and third data storage units. A second data transfer circuit is connected between the second and third data storage units. The second data storage unit has a function of forcibly changing a value of data of the first data storage unit based on the data stored in the second data storage unit.
Claims30
A nonvolatile semiconductor memory comprising:
- a memory cell;
- a bit line connected to one end of the memory cell;
- and
- a data circuit which is connected to the bit line and in which program data or read data concerning the memory cell is temporarily stored,
- wherein the data circuit includes:
- first, second, and third data storage units;
- a first data transfer circuit connected between the first and third data storage units;
- and a second data transfer circuit connected between the second and third data storage units, and
- the first data storage unit is connected to the bit line, and the second data storage unit includes a function of forcibly changing data of the first data storage unit based on the data stored in the second data storage unit.
A nonvolatile semiconductor memory comprising:
- a nonvolatile semiconductor memory cell which can electrically be rewritten;
- a bit line connected to the memory cell;
- a read circuit which reads out data of the memory cell and which includes a first data storage unit connected to the bit line, a second data storage unit having a function of forcibly changing the data of the first data storage unit in accordance with the data stored in the second data storage unit, a third data storage unit having a function of reading out the data of the first data storage unit, and a data transfer circuit to transfer the data of the third data storage unit to the second data storage unit;
- and
- a read control circuit which reads the data of the memory cell into the first data storage unit via the bit line, forcibly changes the read data of the first data storage unit in accordance with the data of the second data storage unit, subsequently transfers the data of the third data storage unit to the second data storage unit, and further subsequently reads out the data of the first data storage unit by the third data storage unit.
Dependencies are inferred from the claim text.