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US 2004/0174736 A1Published application
Semiconductor memory device
AssigneeOki Electric Industry Co., Ltd.
InventorTakashi Takemura
Life of this patent
Estimating the term…
Abstract
There is an SRAM which can perform a high-speed read operation at a low power supply voltage and which can simplify a circuit configuration and manufacturing steps. When signals at levels “H” and “L” are output from a flip-flop to storage nodes, respectively, the threshold voltages of first and second N-channel MOS transistors having channel regions connected to the storage node decrease to improve the current drive capabilities of the transistors. The second N-channel MOS transistor is set in an ON state by the level of the storage node. In this case, when a word line goes to level “H”, the first N-channel MOS transistor is turned on, and a bit line is drawn in a ground potential at a high speed.
Claims13
A semiconductor memory device comprising:
- first and second bit lines for inputting/outputting complementary data;
- a first transistor for controlling connection between a first storage node and the first bit line on the basis of a selection signal;
- a second transistor for controlling connection between a second storage node and the second bit line on the basis of the selection signal;
- a flip-flop for holding potentials of the first and second storage nodes to output the potentials;
- a third transistor, having a channel region given the same potential of the second storage node, to control connection between a first internal node and the first bit line on the basis of the selection signal;
- a fourth transistor, having a channel region given the same potential of the second storage node, to control connection between a common potential and the first internal node on the basis of the potential of the second storage node;
- a fifth transistor, having a channel region given the same potential of the first storage node, to control connection between a second internal node and the second bit line on the basis of the selection signal;
- and
- a sixth transistor, having a channel region given the same potential of the first storage node, to control connection between the common potential and the second internal node on the basis of the potential of the first storage node.
6 more elements
A semiconductor memory device comprising:
- first and second bit lines for inputting/outputting complementary data;
- a first transistor to control connection between a first storage node and the first bit line on the basis of a selection signal;
- a second transistor to control connection between a second storage node and the second bit line on the basis of the selection signal;
- a flip-flop for holding potentials of the first and second storage nodes to output the potentials;
- a third transistor, having a channel region given the same potential of the second storage node, to connect a first internal node to the first bit line in a data read state;
- a fourth transistor, having a channel region given the same potential of the second storage node, to control connection between a common potential and the first internal node on the basis of the potential of the second storage node;
- a fifth transistor, having a channel region given the same potential of the first storage node, to connect a second internal node to the second bit line in a data read state;
- and
- a sixth transistor, having a channel region given the same potential of the first storage node, to control connection between the common potential and the second internal node on the basis of the potential of the first storage node.
6 more elements
A semiconductor memory device comprising:
- first and second bit lines for inputting/outputting complementary data;
- a first transistor to control connection between a first storage node and the first bit line on the basis of a selection signal;
- a second transistor to control connection between a second storage node and the second bit line on the basis of the selection signal;
- a flip-flop for holding potentials of the first and second storage nodes to output the potentials;
- a third transistor, having a channel region given the same potential of the second storage node, to connect a first internal node to the first bit line in a data read state;
- a fourth transistor, having a channel region given the same potential of the second storage node, to control connection between a common potential and the first internal node on the basis of the potential of the second storage node;
- a fifth transistor, having a channel region given the same potential of the first storage node, to connect a second internal node to the second bit line in a data read state;
- a sixth transistor, having a channel region given the same potential of the first storage node, to control connection between the common potential and the second internal node on the basis of the potential of the first storage node;
- a word line connected to the first and second transistors;
- a signal line connected to the third and fifth transistors;
- a logical circuit for outputting the selection signal to the word line when data is written in the flip-flop and for outputting a control signal for controlling the third and fifth transistors to the signal line in the data read state.
8 more elements
Dependencies are inferred from the claim text.