US 2004/0174735 A1Published application

Semiconductor memory circuit

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorMasashi Agata

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Abstract

Data reading speed of a DRAM is enhanced without causing an increase in the power consumption and in the chip area. To that end, when data is read, a pair of bit lines is precharged to a GND level, while a dummy cell is charged at a power supply voltage. Immediately after a word line and a dummy word line are activated and their respective potentials are increased by the threshold voltage of an access transistor, a main capacitor and a dummy capacitor are electrically connected to the bit lines, thereby allowing the data to fade in. The resultant potential difference between the pair of bit lines is detected and amplified by a sense amplifier, thereby enabling the data to be read. The capacitance of the dummy capacitor is about half of that of the main capacitor, so that the dummy capacitor can be precharged at the power supply voltage.

Claims16

Dependent claims

A semiconductor memory circuit comprising:

a memory cell that includes
a first capacitor for storing therein electric charge corresponding to stored data, and
a first transistor whose gate is connected to a word line and one of whose source and drain is connected to a first bit line, while the other of whose source and drain is connected to the first capacitor;
a dummy cell that includes
a second capacitor having smaller capacitance than the first capacitor,
a second transistor whose gate is connected to a dummy word line, and one of whose source and drain is connected to a second bit line, while the other of whose source and drain is connected to the second capacitor, and
a third transistor for electrically connecting the second capacitor with a voltage line in accordance with a precharge signal when the dummy word line is inactive, the voltage line supplying a first voltage;
a precharge circuit for precharging the first and second bit lines to a second voltage when the word line and the dummy word line are inactive;
and
a sense amplifier for detecting a potential difference caused between the first and second bit lines when the word line and the dummy word line are activated to electrically connect the first and second capacitors to the first and second bit lines, respectively, and for amplifying the voltages of the first and second bit lines either to the first voltage and to the second voltage, or to the second voltage and to the first voltage, respectively,
wherein the transitions of the word line and the dummy word line from the inactivation voltage level to the activation voltage level are both in a direction from the second voltage to the first voltage.

8 more elements

A semiconductor memory circuit comprising:

a memory cell that includes
a first capacitor for storing therein electric charge corresponding to stored data, and
a first transistor whose gate is connected to a word line and one of whose source and drain is connected to a first bit line, while the other of whose source and drain is connected to the first capacitor;
a dummy cell that includes
a second capacitor,
a second transistor whose gate is connected to a dummy word line, and one of whose source and drain is connected to a second bit line, while the other of whose source and drain is connected to the second capacitor, and
a third transistor for electrically connecting the second capacitor with a voltage line in accordance with a precharge signal when the dummy word line is inactive, the voltage line supplying a first voltage;
a precharge circuit for precharging the first and second bit lines to a second voltage when the word line and the dummy word line are inactive;
and
a sense amplifier for detecting a potential difference caused between the first and second bit lines when the word line and the dummy word line are activated to electrically connect the first and second capacitors to the first and second bit lines, respectively, and for amplifying the voltages of the first and second bit lines either to the second voltage and to a third voltage, or to the third voltage and to the second voltage, respectively,
wherein the transitions of the word line and the dummy word line from the inactivation voltage level to the activation voltage level are both in a direction from the second voltage to the third voltage;
and
the amplitude of the dummy word line voltage is smaller than the amplitude of the world line voltage.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/790,135Filed 2 Mar 2004
Priority: JP 2003-0557903 Mar 2003
Published: 9 Sep 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 12/50
Dynamic random access memory [DRAM] devices: peripheral circuit region structures
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 7/14
Arrangements for writing information into, or reading information out from, a digital store: dummy cell management; Sense reference voltage generators
G11C 11/4094
Read-write [R-W] circuits: bit-line management or control circuits