Vertical gain cell
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the sense transistor. Addressing the second vertical MOS transistor provides a means for changing a potential of the floating body of the sense transistor. The vertical gain cell can be used in a memory array with a read data/bit line and a read data word line coupled to the sense transistor, and with a write data/bit line and a write data word line coupled to the second transistor of the vertical gain cell.
Claims77
A vertical gain cell comprising:
- a first vertical MOS transistor configured as a sense transistor with a floating body;
- and
- a second vertical MOS transistor merged with the first vertical MOS transistor, the second vertical MOS transistor coupled to a conductive line, wherein addressing the second vertical MOS transistor couples the floating body to the conductive line.
An electronic apparatus having a vertical gain cell comprising:
- a first vertical MOS transistor configured as a sense transistor with a floating body;
- a second vertical MOS transistor merged with the first vertical MOS transistor;
- and
- a means for controlling the second vertical MOS transistor to change a potential of the floating body.
A vertical gain memory cell comprising:
- a first vertical MOS transistor configured as a sense transistor with a floating body, the first vertical MOS transistor having a gate coupled to a read data word line;
- and
- a second vertical MOS transistor merged with the first vertical MOS transistor, the second vertical MOS transistor coupled to a conductive line, wherein addressing the second vertical MOS transistor couples the floating body to the conductive line.
A memory comprising:
- an array of vertical gain memory cells;
- a number of read data word lines;
- and
- a number of write data/bit lines, wherein each vertical gain memory cell includes:
- a first vertical MOS transistor configured as a sense transistor with a floating body, the first vertical MOS transistor having a gate coupled to a read data word line;
- and
- a second vertical MOS transistor merged with the first vertical MOS transistor, the second vertical MOS transistor coupled to a write data/bit line, wherein addressing the second vertical MOS transistor couples the floating body to the write data/bit line.
An electronic apparatus comprising:
- a processor;
- and
- a memory operably coupled to the processor, the memory having:
- an array of vertical gain memory cells;
- a number of read data word lines;
- and
- a number of write data/bit lines, wherein each vertical gain memory cell includes:
- a first vertical MOS transistor configured as a sense transistor with a floating body, the first vertical MOS transistor having a gate coupled to a read data word line;
- and
- a second vertical MOS transistor merged with the first vertical MOS transistor, the second vertical MOS transistor coupled to a write data/bit line, wherein addressing the second vertical MOS transistor couples the floating body to the write data/bit line.
A method of operating a vertical gain cell comprising:
- applying a signal to a conductive line coupled to the vertical gain cell, the vertical gain cell including a first vertical MOS transistor having a floating body and a second vertical MOS transistor merged with the first vertical MOS transistor, the second vertical MOS coupled to the conductive line;
- and
- addressing the second vertical MOS transistor to operatively couple the floating body to the conductive line.
A method of forming a vertical gain cell comprising:
- forming a first vertical MOS transistor having a floating body;
- and
- forming a second vertical MOS transistor merged with the first vertical MOS transistor, and
- coupling the second vertical MOS transistor to a conductive line such that addressing the second vertical MOS transistor couples the floating body to the conductive line.
A method of forming a memory comprising:
- forming a number of read data word lines;
- forming a number of write data word lines;
- forming a number of write data/bit lines;
- and
- forming a number of vertical gain memory cells, each vertical memory cell coupled to one of the number of read data word lines and one of the write data word lines, wherein forming each vertical gain memory cell includes:
- forming a first vertical MOS transistor having a floating body;
- and
- forming a second vertical MOS transistor merged with the first vertical MOS transistor, and
- coupling the second vertical MOS transistor to a write data/bit line such that addressing the second vertical MOS transistor operatively couples the floating body to the write data/bit line.
A method of forming an electronic apparatus comprising:
- providing a processor;
- and
- coupling the processor to a memory, the memory formed by a method including:
- forming a number of read data word lines;
- forming a number of write data word lines;
- forming a number of write data/bit lines;
- and
- forming a number of vertical gain memory cells, each vertical memory cell coupled to one of the number of read data word lines and one of the write data word lines, wherein forming each vertical gain memory cell includes:
- forming a first vertical MOS transistor having a floating body;
- and
- forming a second vertical MOS transistor merged with the first vertical MOS transistor, and
- coupling the second vertical MOS transistor to a write data/bit line such that addressing the second vertical MOS transistor operatively couples the floating body to the write data/bit line.
Dependencies are inferred from the claim text.