Structure and System-on-Chip Integration of a Two-Transistor and Two-Capacitor Memory Cell for Trench Technology

A system on-chip comprising a first memory cell, comprising a 1-port memory cell formed by one transistor and one trench capacitor, wherein said one transistor is controlled by a wordline that selectively couples a storage node of said trench capacitor to a bitline;

• and
• a 2-port memory cell comprising two memory cells, each having one transistor and one trench capacitor to selectively couple a storage node of said trench capacitor to a bitline, wherein two storage nodes of said two memory cells are linked to each other to form a common storage node, allowing access of a data bit in said common storage node of said trench capacitors through said one transistor of either one of said two 1-port memory cells.

A system-on chip comprising:

• a first 1-port memory cell and a 2-port memory cell, said first 1-port memory cell comprising a first transistor and first trench capacitor to selectively access a storage node of said first trench capacitor to a bitline through said first transistor that controls a wordline, and said 2-port memory cell comprising two second 1-port memory cells, each having a second transistor and second trench capacitor that selectively couple a storage node of said second trench capacitor to a bitline, said two storage nodes of said two memory cells are connected to each other to form a common storage node, allowing access of a data bit in said common storage node through second transistor of either one of said second transistor of said two second 1-port memory cells, wherein said first and second 1-port memory cell of said 2-port memory cell have the same structure.