Loading patent…
AssigneeHitachi, Ltd.
InventorsRyuichi Saito, Hidekatsu Onose, Yutaka Kobayashi, Michio Ohue
Estimating the term…
A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.
A semiconductor memory device having at least one memory cell, said at least one memory cell including a switching element and a capacitive element connected in series with said switching element, wherein said capacitive element has a ferroelectric body, and the polarization axis of said ferroelectric body is substantially parallel to a predetermined direction of an electric field across said capacitive element, and wherein said capacitive element is provided above said switching element.
A semiconductor memory device having at least one memory cell, said at least one memory cell including a switching element, said switching element having a first electrode, a second electrode and a gate electrode, and a capacitive element connected to said first electrode in series with said switching element, wherein said capacitive element has a ferroelectric body, and the polarization axis of said ferroelectric body is substantially parallel to a predetermined direction of an electric field across said capacitive element, and wherein said ferroelectric body is provided above said first electrode.
A method of controlling an engine which is coupled to a microprocessor, and I/O control and a memory, wherein said memory includes a switching element and a capacitive element connected in series with said switching element, wherein said capacitive element has a ferroelectric body, and the polarization axis of said ferroelectric body is substantially parallel to a predetermined direction of an electric field across said capacitive element, and wherein said capacitive element is provided above said switching element, said method comprising:
Dependencies are inferred from the claim text.