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US 2004/0174729 A1Published application
Memory
AssigneeSanyo Electric Co., Ltd.
InventorsNaofumi Sakai, Yoh Takano
Life of this patent
Estimating the term…
Abstract
A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.
Claims35
A memory comprising:
- a bit line;
- a word line arranged to intersect with said bit line;
- and
- first storage means connected between said bit line and said word line for holding first data or second data, and
- applying a voltage pulse supplying an electric field in a first direction and another voltage pulse supplying another electric field in a direction opposite to said first direction to at least non-selected said first storage means other than selected said first storage means connected to selected said word line substantially identical times respectively or substantially applying no voltage pulse through a read operation and a rewrite operation consisting of a plurality of operations performed on said selected first storage means.
2 more elements
A memory comprising:
- a bit line;
- a word line arranged to intersect with said bit line;
- and
- first storage means connected between said bit line and said word line for holding first data or second data, and
- performing no rewrite operation when data read in a read operation performed on selected said first storage means connected to selected said word line is identical to data held in said selected first storage means after said read operation.
2 more elements
A memory comprising:
- a bit line;
- a word line arranged to intersect with said bit line;
- and
- first storage means connected between said bit line and said word line for holding first data or second data, and
- applying a voltage pulse supplying an electric field in a first direction and another voltage pulse supplying another electric field in a direction opposite to said first direction to at least non-selected said first storage means other than selected said first storage means connected to selected said word line substantially identical times respectively or substantially applying no voltage pulse through a write operation consisting of at least one operation performed on said selected first storage means.
2 more elements
A memory comprising:
- a bit line;
- a word line arranged to intersect with said bit line;
- and
- first storage means connected between said bit line and said word line for holding first data or second data, and
- completing a write operation with one operation when data to be written in selected said first storage means connected to selected said word line is substantially only said first data or said second data while completing said write operation with a plurality of operations when said data to be written is substantially not only said first data or said second data.
2 more elements
Dependencies are inferred from the claim text.