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US 2004/0174726 A1Published application
Semiconductor memory device, and semiconductor device with the semiconductor memory device and logic circuit device therein
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsToshihiro Nakamura, Kiyoto Ota, Masahisa Iida, Kenichi Origasa
Life of this patent
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Abstract
There is provided a semiconductor memory device in which a bit line precharge operation is increased in speed, and a layout area is reduced. P-channel transistors (206, 207) that function as switches are provided in a precharge voltage pumping circuit (105) included in a bit line precharge voltage generation unit. This enhances a pumping efficiency, and reduces a capacitance area of a pumping capacitor (200).
Claims43
A semiconductor memory device, comprising:
- a plurality of memory cells;
- paired bit lines connected to the plurality of memory cells;
- a plurality of precharge circuits for precharging the paired bit lines to a predetermined precharge voltage in accordance with a first control signal;
- and a bit line precharge voltage generation unit for supplying a voltage for precharging to the plurality of precharge circuits, an equalizing voltage of the paired bit lines being different from the precharge voltage,
- the bit line precharge voltage generation unit comprising:
- a precharge voltage generation circuit for generating the precharge voltage and supplying the precharge voltage to the plurality of precharge circuits;
- and
- a precharge voltage pumping circuit including a pumping capacitor, a first switch for connecting a first electrode of the pumping capacitor to a first power source, a second switch for connecting the first electrode to an output node of the precharge voltage generation circuit, a third switch for connecting a second electrode of the pumping capacitor to the first power source, a fourth switch for connecting the second electrode to a second power source, and a control circuit for controlling on/off of the first, second, third, and fourth switches.
5 more elements
A semiconductor memory device, comprising:
- a plurality of memory cells;
- paired bit lines connected to the plurality of memory cells;
- a plurality of precharge circuits for precharging the paired bit lines to a predetermined precharge voltage in accordance with a first control signal;
- and a bit line precharge voltage generation unit for supplying a voltage for precharging to the plurality of precharge circuits, an equalizing voltage of the paired bit lines being different from the precharge voltage,
- the bit line precharge voltage generation unit comprising:
- a precharge voltage generation circuit for generating the precharge voltage and supplying the precharge voltage to the plurality of precharge circuits;
- and
- a precharge voltage pumping circuit including a pumping capacitor, a first switch for connecting a first electrode of the pumping capacitor to a first power source, a second switch for connecting the first electrode to an output node of the precharge voltage generation circuit, and a control circuit for controlling on/off of the first and second switches, wherein a second electrode of the pumping capacitor is driven with a second control signal.
5 more elements
A semiconductor memory device, comprising:
- a plurality of memory cells;
- paired bit lines connected to the plurality of memory cells;
- a plurality of precharge circuits for precharging the paired bit lines to a predetermined precharge voltage in accordance with a first control signal;
- and a bit line precharge voltage generation unit for supplying a voltage for precharging to the plurality of precharge circuits, an equalizing voltage of the paired bit lines being different from the precharge voltage,
- the bit line precharge voltage generation unit comprising:
- a precharge voltage generation circuit for generating the precharge voltage and supplying the precharge voltage to the plurality of precharge circuits;
- and
- a precharge voltage pumping circuit including a pumping capacitor, a first switch for connecting a first electrode of the pumping capacitor to a first power source, a second switch for connecting the first electrode to an output node of the precharge voltage generation circuit, and a control circuit for controlling on/off of the first and second switches, wherein a second electrode of the pumping capacitor is driven with a second control signal,
- wherein the second control signal rises during an activation period of a first control signal that is a bit line precharge starting signal to the precharge circuit.
6 more elements
A semiconductor memory device, comprising:
- a plurality of memory cells;
- paired bit lines connected to the plurality of memory cells;
- a plurality of precharge circuits for precharging the paired bit lines to a predetermined precharge voltage in accordance with a first control signal;
- and a bit line precharge voltage generation unit for supplying a voltage for precharging to the plurality of precharge circuits, an equalizing voltage of the paired bit lines being different from the precharge voltage,
- the bit line precharge voltage generation unit comprising:
- a precharge voltage generation circuit for generating the precharge voltage and supplying the precharge voltage to the plurality of precharge circuits;
- and
- a precharge voltage pumping circuit including a pumping capacitor, a first switch for connecting a first electrode of the pumping capacitor to a first power source, a second switch for connecting the first electrode to an output node of the precharge voltage generation circuit, a control circuit for controlling on/off of the first and second switches, and a precharge voltage pumping circuit for driving a second electrode of the pumping capacitor with a second control signal,
- wherein the second control signal rises with a transition time longer than a transition time of the first control signal, after a predetermined delay time from activation of the first control signal that is a bit line precharge starting signal to the precharge circuit.
6 more elements
A semiconductor device with a semiconductor memory device and a logic circuit device therein,
- wherein the semiconductor memory device includes:
- a plurality of memory cells;
- paired bit lines connected to the plurality of memory cells;
- a plurality of precharge circuits for precharging the paired bit lines to a predetermined precharge voltage in accordance with a first control signal;
- and a bit line precharge voltage generation unit for supplying a voltage for precharging to the plurality of precharge circuits, an equalizing voltage of the paired bit lines being different from the precharge voltage,
- the bit line precharge voltage generation unit includes:
- a precharge voltage generation circuit for generating the precharge voltage and supplying the precharge voltage to the plurality of precharge circuits;
- and
- a precharge voltage pumping circuit including a pumping capacitor, a first switch for connecting a first electrode of the pumping capacitor to a first power source, a second switch for connecting the first electrode to an output node of the precharge voltage generation circuit, a control circuit for controlling on/off of the first and second switches, and a precharge voltage pumping circuit for driving a second electrode of the pumping capacitor with a second control signal, and
- a voltage amplitude of the second control signal is substantially the same as a voltage amplitude of a signal in the logic circuit device.
7 more elements
A semiconductor device with a semiconductor memory device and a logic circuit device therein,
- wherein the semiconductor memory device includes:
- a plurality of memory cells;
- paired bit lines connected to the plurality of memory cells;
- a plurality of precharge circuits for precharging the paired bit lines to a predetermined precharge voltage in accordance with a first control signal;
- and a bit line precharge voltage generation unit for supplying a voltage for precharging to the plurality of precharge circuits, an equalizing voltage of the paired bit lines being different from the precharge voltage,
- the bit line precharge voltage generation unit includes:
- a precharge voltage generation circuit for generating the precharge voltage and supplying the precharge voltage to the plurality of precharge circuits;
- and
- a precharge voltage pumping circuit including a pumping capacitor, a first switch for connecting a first electrode of the pumping capacitor to a first power source, a second switch for connecting the first electrode to an output node of the precharge voltage generation circuit, a control circuit for controlling on/off of the first and second switches, and a precharge voltage pumping circuit for driving a second electrode of the pumping capacitor with a second control signal,
- the second control signal rises during an activation period of a first control signal that is a bit line precharge starting signal to the precharge circuit, and
- a voltage amplitude of the second control signal is substantially the same as a voltage amplitude of a signal in the logic circuit device.
8 more elements
A semiconductor device with a semiconductor memory device and a logic circuit device therein,
- wherein the semiconductor memory device includes:
- a plurality of memory cells;
- paired bit lines connected to the plurality of memory cells;
- a plurality of precharge circuits for precharging the paired bit lines to a predetermined precharge voltage in accordance with a first control signal;
- and a bit line precharge voltage generation unit for supplying a voltage for precharging to the plurality of precharge circuits, an equalizing voltage of the paired bit lines being different from the precharge voltage,
- the bit line precharge voltage generation unit includes:
- a precharge voltage generation circuit for generating the precharge voltage and supplying the precharge voltage to the plurality of precharge circuits;
- and
- a precharge voltage pumping circuit including a pumping capacitor, a first switch for connecting a first electrode of the pumping capacitor to a first power source, a second switch for connecting the first electrode to an output node of the precharge voltage generation circuit, a control circuit for controlling on/off of the first and second switches, and a precharge voltage pumping circuit for driving a second electrode of the pumping capacitor with a second control signal,
- the second control signal rises with a transition time longer than a transition time of the first control signal, after a predetermined delay time from activation of the first control signal that is a bit line precharge signal to the precharge circuit, and
- a voltage amplitude of the second control signal is substantially the same as a voltage amplitude of a signal in the logic circuit device.
8 more elements
Dependencies are inferred from the claim text.