# US 2004/0173878 A1 · Method and apparatus for accessing internal nodes of an integrated circuit using ic package substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2004/0173878 A1 - Document ID: US20040173878A1 - Status: Published application - Kind: A1 - Application number: 10/382,343 - Filed: 2003-03-04 - Published: 2004-09-09 - Earliest claimed: 2003-03-04 - Assignees: NPTest, LLC - Inventors: Kenneth Wilsher - Web page: https://patentgrep.com/patent/US20040173878A1 ## CPC - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 70/655: Fan-out layouts - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method and apparatus for accessing internal nodes of an integrated circuit using a package substrate are provided. Embodiments of the present invention include an integrated circuit comprising an integrated circuit die comprising a principal side; a conductive element formed on the principal side of the integrated circuit die; a package substrate comprising a principal side facing the principal side of the integrated circuit die; a conductive element located on the principal side of the package substrate; a transmission path wherein a first end of the transmission path is coupled to the conductive element of the integrated circuit die and wherein a second end of the transmission path is coupled to the conductive element of the package substrate. ## Claims ### Claim 1 1) An integrated circuit comprising: an integrated circuit die comprising a principal side and having an internal circuit node; a conductive element formed on said principal side of said integrated circuit die and coupled to said internal circuit node; a package substrate comprising a principal side facing said principal side of said integrated circuit die; a conductive element mounted on said principal side of said package substrate and externally accessible to an integrated circuit testing apparatus; a transmission path wherein a first end of said transmission path is coupled to said conductive element of said integrated circuit die and wherein a second end of said transmission path is coupled to said externally accessible conductive element of said package substrate. ### Claim 2 (depends on 1) 2) The integrated circuit as described in claim 1 wherein signals are transferred from said internal circuit node of said integrated circuit to said conductive element of said package substrate via said transmission path. ### Claim 3 (depends on 1) 3) The integrated circuit as described in claim 1 wherein signals are transferred from said conductive element of said package substrate to said internal node via said transmission path. ### Claim 4 (depends on 1) 4) The integrated circuit as described in claim 1 further comprising a plurality of internal circuit nodes; a plurality of transmission paths, coupled to said plurality of internal nodes; and a plurality of externally accessible conductive elements mounted on said principal surface of said package substrate and coupled to said plurality of transmission paths. ### Claim 5 (depends on 1) 5) The integrated circuit as described in claim 1 wherein signals are transferred from a plurality of internal circuit nodes of said integrated circuit die to said conductive element of said package substrate via said transmission path. ### Claim 6 (depends on 1) 6) The integrated circuit as described in claim 1 further comprising a plurality of conductive elements mounted on said principal side of said package substrate and externally accessible to said integrated circuit testing apparatus, and a plurality of transmission paths wherein said plurality of transmission paths are coupled to said plurality of said conductive elements of said package substrate. ### Claim 7 (depends on 6) 7) The integrated circuit as described in claim 6 further comprising a signal selector coupled to said internal circuit node wherein signals from said internal circuit node are selectably coupleable to said plurality of conductive elements of said package substrate. ### Claim 8 (depends on 7) 8) The integrated circuit as described in claim 7 further comprising an adjustable clock delay operable to capture said signals from said internal nodes at an adjustable time. ### Claim 9 (depends on 6) 9) The integrated circuit as described in claim 6 further comprising a buffer coupled to said internal circuit node. ### Claim 10 (depends on 9) 10) The integrated circuit as described in claim 9 wherein said internal circuit node is coupled to a shift register. ### Claim 11 (depends on 10) 11) The integrated circuit as described in claim 10 further comprising a latch coupled to said internal node. ### Claim 12 (depends on 1) 12) The integrated circuit as described in claim 1 wherein a portion of said package substrate extends past an edge of said integrated circuit die and wherein said conductive element extends past an edge of said integrated circuit die. ### Claim 13 13) An integrated circuit comprising: an integrated circuit die comprising a principal side; a buffer comprising an input terminal coupled to an internal circuit node of said integrated circuit die; a conductive element formed on said principal side of said circuit die coupled to an output terminal of said buffer; a multi-layer package substrate comprising a principal side facing said principal side of said integrated circuit die; a transmission path on a layer of said package substrate, wherein a first end of said transmission path is coupled to said conductive element of said circuit die; and an externally accessible conductive region on said principal side of said package substrate coupled to a second end of said transmission path. ### Claim 14 (depends on 13) 14) The integrated circuit as described in claim 13 further comprising a plurality of internal circuit nodes coupled to a corresponding plurality of transmission paths. ### Claim 15 (depends on 13) 15) The integrated circuit as described in claim 13 wherein said internal circuit node is coupled to a shift register. ### Claim 16 (depends on 15) 16) The integrated circuit as described in claim 15 further comprising a latch coupled to said internal circuit node. ### Claim 17 (depends on 13) 17) The integrated circuit as described in claim 13 wherein said conductive element is a deformable ball bond. ### Claim 18 (depends on 13) 18) The integrated circuit as described in claim 13 wherein said package substrate is a multi-layered insulative structure comprising a plurality of conductive paths. ### Claim 19 (depends on 13) 19) The integrated circuit as described in claim 13 wherein a portion of said package substrate comprises a plurality of conductive regions and wherein said portion extends past an edge of said integrated circuit die. ### Claim 20 (depends on 13) 20) The integrated circuit as described in claim 13 wherein a transmission path comprises at least one conductive via in said package substrate substantially perpendicular to said principal side of said package substrate. ### Claim 21 (depends on 13) 21) The integrated circuit as described in claim 13 further comprising a heat sink thermally coupled to said integrated circuit die. ### Claim 22 (depends on 13) 22) The integrated circuit as described in claim 13 wherein said transmission path has an impedance in the range of approximately 45 to 55 ohms. ### Claim 23 23) A method for testing an integrated circuit comprising: mounting a principal surface of an integrated circuit die to a package substrate comprising an externally accessible contact pads wherein at least one internal circuit node of said integrated circuit die is electrically coupled to said externally accessible contact pads by an electrical transmission path; and electrically coupling a test apparatus to said externally accessible contact pads. ### Claim 24 (depends on 23) 24) The method as described in claim 23 further comprising selecting one of said at least one internal circuit nodes of said integrated circuit to be coupled to said externally accessible contact pads by said electrical transmission path. ### Claim 25 (depends on 23) 25) The integrated circuit as described in claim 23 wherein signals are transferred from one of said at least one internal circuit nodes to said externally accessible contact pads via said transmission path. ### Claim 26 (depends on 25) 26) The method as described in claim 25 wherein said signals are split from said internal circuit node over a plurality of electrical transmission paths coupled to a corresponding plurality of contact pads on said package substrate package to said test apparatus. ### Claim 27 (depends on 23) 27) The method as described in claim 23 wherein signals are transferred from said test apparatus to one of said at least one internal circuit nodes of said integrated circuit via said externally accessible contact pads and via said electrical transmission path.