External storage device and memory access control method thereof

An external storage device comprising:

• a system interface section for conducting interface with a host computer;
• a memory for storing sector data, and having a memory bus with a memory bus width which is twice a width of a system bus;
• error correcting means for performing error detection and error correction for said sector data;
• and
• control means for controlling a reading and writing operation of sector data with respect to said memory;
• wherein in response to a write command from said host computer, said control means stores odd-numbered sector data pertaining to the write command in memory locations accessed by one of an upper side and a lower side of said memory bus, and also stores even-numbered sector data pertaining to the write command in memory locations accessed by an opposite one of said upper side and said lower side of said memory bus, and
• in response to a read command from said host computer, said control means reads out-a first sector data among a plurality of sector data required by the read command using one of said upper side and said lower side of said memory bus, and supplies a read-out sector data to said error correcting means, and then said control means reads out sector data using both of said upper side and said lower side of said memory bus simultaneously, so that while N-th (where N is a natural number) sector data from one of said upper side and said lower side of said memory bus are transferred to said system interface section, (N+1)th sector data from the other are transferred to said error correcting means.

A memory access control method of an external storage device having:

• a system interface section for conducting interface with a host computer;
• a first memory storage area and a second memory storage area for storing sector data;
• error correcting means for performing error detection and error correction for said sector data;
• said method comprising the steps of:
• storing, in response to a write command from a host computer, a plurality of sector data pertaining to said write command in sector units alternately in said first memory storage area and said second memory storage area;
• and
• reading, in response to a read command from said host computer, a first sector data among a plurality of sector data required by the read command from one of said first memory storage area and said second memory storage area, and supplying a read-out sector data to said error correcting means, and then reading out sector data of said first memory storage area and said second memory storage area simultaneously, so that while N-th (where N is a natural number) sector data from one of said first memory storage area and said second memory storage area are transferred to said system interface section, (N+1)th sector data from the other are transferred to said error correcting means.

A memory access control method of an external storage device having:

• a system interface section for conducting interface with a host computer;
• a memory for storing sector data, and having a memory bus with a memory bus width which is twice a width of a system bus;
• error correcting means for performing error detection and error correction for said sector data;
• said method comprising the steps of:
• storing, in response to a write command from a host computer, odd-numbered sector data pertaining to the write command in memory locations accessed by one of an upper side and a lower side of said memory bus, and even-numbered sector data pertaining to the write command in memory locations accessed by an opposite one of said upper side and said lower side of said memory bus;
• and
• reading, in response to a read command from said host computer, a first sector data among a plurality of sector data required by the read command-using one of said upper side and said lower side of said memory bus, and supplying a read-out sector data to said error correcting means, and then reading out sector data using both of said upper side and said lower side of said memory bus simultaneously, so that while N-th (where N is a natural number) sector data from one of said upper side and said lower side of said memory bus are transferred to said system interface section, (N+1)th sector data from the other are transferred to said error correcting means.