Buffer circuit and method
AssigneeHewlett-Packard Development Company, L.P.
InventorDerek A. Sherlock
Life of this patent
Estimating the term…
Abstract
The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit comprising circuitry to latch the data signal with the first clock signal to produce a first latched signal, circuitry to latch the data signal with the second clock signal to produce a second latched signal, and circuitry that selects the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle.
Claims22
A buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit comprising:
- circuitry to latch the data signal with the first clock signal to produce a first latched signal;
- circuitry latch the data signal with the second clock signal to produce a second latched signal;
- and
- circuitry to select the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle:
A buffer circuit to receive a data signal, a first clock signal and a second clock signal, the buffer circuit comprising:
- means for latching the data signal with the first clock signal to produce a first latched signal;
- means for latching the data signal with the second clock signal to produce a second latched signal;
- and
- means for selecting the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle:
A computer system having at least one integrated circuit component that comprises a buffer circuit, the buffer circuit operable to receive a data signal, a first clock signal and a second clock signal, the buffer circuit comprising:
- circuitry to latch the data signal with the first clock signal to produce a first latched signal;
- circuitry to latch the data signal with the second clock signal to produce a second latched signal;
- and
- circuitry to select the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle:
A method of operating a buffer circuit to receive a data signal, a first clock signal and a second clock signal, the method comprising:
- receiving a data signal;
- storing a first latched data signal using a first clock signal that transitions in a first direction;
- storing a second latched data signal using a second clock signal that transitions in a second direction;
- latching the data signal with the first clock signal if the data signal has transitioned in the first direction;
- and
- latching the data signal with the second clock signal if the data signal has transitioned in the second direction.
Dependencies are inferred from the claim text.