Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section

A method for minimizing skew between address, clock and data signals on respective address, clock and data buses extending between an address/clock generation block and a data output block in an integrated circuit memory device, said method comprising:

• selectively placing a first predetermined number of signal delays on said address and clock buses between said address/clock generation block and each of preselected ones of memory arrays of said memory device coupled to said data bus;
• and
• selectively placing a second predetermined number of signal delays on said data bus between each of said preselected ones of said memory arrays such that a total of said first and second predetermined number of said signal delays on said address, clock and data buses from said address/clock generation block to said data output block is substantially a constant for each of said memory arrays.

A technique for minimizing skew between clock and data signals at a data output block of an integrated circuit memory device comprising a plurality of memory arrays, said technique comprising:

• selectively adding delays to address and clock information buses coupled to said memory arrays such that a cumulative delay to signals generated on said address and clock information buses increases as a position of each of said memory arrays becomes more distal from an address/clock generation block;
• and
• selectively adding delays to a data bus coupled to said memory arrays such that a cumulative delay to signals output on said data bus decreases as a position of each of said memory arrays becomes more proximate to said data output block such that a total delay added to said address, clock information and data buses for each of said memory arrays is substantially constant.