Apparatus and method for performing a detached load operation in a pipeline microprocessor

A pipeline microprocessor, comprising:

• a data cache, coupled to a bus;
• a plurality of execution units, each coupled to said data cache by said bus, each having an instruction queue and dispatch logic for dispatching instructions from said queue to a functional unit of the execution unit for execution thereof after said instruction queue indicates all operands of the instructions are valid;
• and
• an instruction dispatcher, coupled to said plurality of execution units, configured to provide to said instruction queues of said plurality of execution units instructions and operands thereof and an indication of whether said operands are valid, wherein if an instruction operand is unavailable from said data cache, said instruction dispatcher provides said instruction to said instruction queue with an indication that said unavailable operand is invalid, rather than stalling subsequent instructions in the pipeline to wait for said operand from said data cache.

A method for performing distributed load instruction dispatching in a pipeline microprocessor having a cache, a central instruction dispatcher and a plurality of execution units each having auxiliary instruction dispatching logic, the method comprising:

• receiving, by the central instruction dispatcher, from the cache an indication that operand data specified by a load instruction is unavailable;
• providing, by the central instruction dispatcher, the load instruction to one of the plurality of execution units and indicating that the data is unavailable;
• and
• obtaining, by the auxiliary instruction dispatching logic in the one of the plurality of execution units, the operand data from the cache subsequent to said indicating to the one of the plurality of execution units that the data is unavailable.

A method for performing detached operand load operations in a microprocessor, the method comprising:

• decoding a first instruction, the first instruction specifying an operand specified by a memory address;
• providing the first instruction to a first execution unit without the operand in response to the memory address missing in the cache memory and indicating to the first execution unit that the operand is invalid;
• obtaining, by the first execution unit, the operand from the cache memory subsequent to said providing the first instruction;
• executing, by the first execution unit, the instruction in response to said obtaining;
• decoding a second instruction after said decoding the first instruction;
• and
• providing the second instruction to a second execution unit prior to said obtaining the operand from the cache memory.

A computer data signal embodied in a transmission medium, comprising:

• computer-readable program code for providing n apparatus in a pipeline microprocessor for avoiding a pipeline stall caused by a load instruction, the microprocessor including execution units, said program code comprising:
• first program code for providing first dispatch logic, configured to request from a cache data specified by the load instruction, to receive from said cache an indication that said data is not presently available from said cache, and to provide the load instruction and a tag identifying said unavailable data for execution to one of the execution units;
• and
• second program code for providing second dispatch logic in each of the execution units, coupled to said cache, configured to monitor a bus coupling said cache and the execution units to detect a valid match of said tag which indicates said data is now available from said cache, to obtain said data from said cache in response to detecting said valid match of said tag, and to dispatch the load instruction and said data in response to obtaining said data from said cache.