Processor, system LSI circuit, method of designing same, and recording medium having said method recorded thereon
AssigneeNEC Electronics Corporation
InventorHiroyuki Nakajima
Life of this patent
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Abstract
A processor has an instruction set A and an instruction set B. A system instruction decoder decodes a system instruction that specifies the operating mode of the processor, the system instruction not being included in either the instruction set A or the instruction set B. A system instruction execution controller receives a decoded signal from the system instruction decoder, which has decoded an instruction requiring changeover of the instruction set, and sets the value of a instruction mode register. On the basis of the value in the instruction mode register, an instruction set changeover unit selects the instruction set to be used.
Claims22
A processor having a plurality of processor functions for executing each of a plurality of instruction sets, comprising:
- a system instruction decoder, provided separately of the plurality of processor functions, for decoding a system instruction that is not executed by any of the plurality of processor functions;
- and
- a system instruction execution unit for selecting one of the plurality of processor functions in response to said system instruction decoded by said system instruction decoder.
A processor having a pipeline control architecture, said processor comprising:
- a unit for receiving a stage-number setting instruction;
- and
- a unit for setting variably the number of stages in the pipeline control in response to the received stage-number setting instruction.
A method of designing a system LSI circuit having a plurality of processors each having a plurality of processor functions for executing a plurality of instruction sets, said method comprising the steps of:
- (a) dividing system LSI circuit design specifications into hardware design and software design at a function designing stage;
- (b) receiving, as hardware information in hardware design, hardware configurations corresponding to respective ones of the plurality of processors, and the system instruction and the plurality of instruction sets described at an algorithm level;
- and
- (c) performing behavioral synthesis using the hardware information.
A computer-readable recording medium on which is recorded a program for causing a computer to execute designing a system LSI circuit having a plurality of processor functions for executing a plurality of instruction sets, said program comprising the processes of:
- (a) dividing system LSI circuit design specifications into hardware design and software design at a function designing stage;
- (b) receiving, in hardware design, as hardware information, hardware configurations corresponding to respective ones of the plurality of processors, and the system instruction and the plurality of instruction sets described at an algorithm level;
- and
- (c) performing behavioral synthesis using the hardware information.
A processor apparatus comprising:
- an instruction fetch register for storing an instruction fetched;
- a plurality of instruction decoders, each receiving and decoding an instruction of an instruction set associated with said instruction decoder;
- a plurality of instruction execution controllers, each being provided in association with the corresponding instruction decoder, for receiving a decoded result of the instruction by the corresponding instruction decoder for controlling the execution of the instruction;
- an instruction set change over unit for selecting at least one among the plurality of instruction decoders and for supplying an instruction output from said instruction fetch register to the selected instruction decoder;
- a system instruction decoder receiving a predetermined system instruction from instruction fetch register for decoding the predetermined system instruction;
- and
- a system instruction execution controller receiving the decoded result from said system instruction decoder;
- said system instruction execution controller controlling said instruction set change over unit to change over the selection of the plurality of instruction decoders, in accordance with said system instruction decoded by said system instruction decoder, in case said system instruction being an instruction specifying the instruction set to be used among a plurality of instruction sets.
Dependencies are inferred from the claim text.