Serial bus controller using nonvolatile ferroelectric memory
AssigneeHynix Semiconductor Inc.
InventorHee Bok Kang
Life of this patent
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Abstract
A serial bus controller using a nonvolatile ferroelectric memory is provided. The memory controller structure using a nonvolatile ferroelectric register enables control of variable access time according to addresses when data are exchanged through a serial bus. In the serial bus controller according to an embodiment of the present invention, access latency time by addresses is programmed using a nonvolatile ferroelectric register, and address access time is differently controlled depending on the programmed access latency when data are exchanged between a master and a FRAM chip through a serial bus, thereby improving system performance.
Claims20
A serial bus controller using a nonvolatile ferroelectric memory, comprising:
- a sense amplifier buffer unit for amplifying data applied from a plurality of cell array blocks;
- a data bus unit for exchanging data between the plurality of cell array blocks and the sense amplifier buffer unit;
- a data input/output buffer unit for buffering data inputted/outputted in the data bus unit;
- a parallel/serial conversion controller for interconverting serial data inputted corresponding to serial clock signals with parallel data applied from the data input/output buffer unit;
- and
- a write protecting controller for preventing data from being written in a corresponding sector of the plurality of cell array block when a write protecting command is set.
A serial bus controller using a nonvolatile ferroelectric memory, comprising:
- a master for outputting serial data/address corresponding to serial clock signals into a serial bus;
- a FRAM chip for controlling read/write operations of the memory depending on serial data/address and the serial clock signal received through the serial bus;
- and
- a memory controller for controlling a response cycle of the serial clock signal depending on a code programmed in a nonvolatile ferroelectric memory to control access latency time differently according to kinds of address between the master and the FRAM chip.
A serial bus controller using a nonvolatile ferroelectric memory, comprising:
- a memory controller for programming a code to control access latency time differently according to kinds of address in a nonvolatile ferroelectric memory and outputting a response signal to confirm completion of transmission of serial data/address when the serial data/address are transmitted in response to serial clock signals received through a serial bus;
- and
- a FRAM chip for performing read/write operations of the memory during a pulse interval of the response signal,
- wherein the memory controller controls the pulse interval of the response signal with a first cycle when a row address is transmitted, and controls the pulse interval of the response signal with a second cycle shorter than the first cycle when a column address is transmitted.
Dependencies are inferred from the claim text.