Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of addresses
AssigneeVIA Technologies, Inc.
InventorMing-Shi Liou
Life of this patent
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Abstract
A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making the corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, bbuilding asingle bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.
Claims18
A memory address decoding method for determining if a given address is located in one of a plurality of sections, each section having a plurality of memory units and each memory unit having a unique corresponding address, the corresponding address using the binary system, the method comprising:
- making the corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size;
- bbuilding asingle bit-pattern for each section from all corresponding addresses;
- and
- comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.
Amemory address decoding method for determining whether a given address is located in one of a plurality of sections, each section having a plurality of memory units and each memory unit having a unique corresponding address, the corresponding address using the binary system, the method comprising:
- sorting the sections by size so as to make the corresponding address of the section with greater size smaller than the corresponding address of the section with smaller size, and if after ssorting, thesize of a first section is equal to the size of a second section, the first and the second sections capable of being swapped;
- building a single bit-pattern for each section from all corresponding addresses;
- and
- comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine in which one of the sections the given address is located based on the comparison.
A control circuit of memory address decoding for determining whether a given address is located in one of a plurality of sections, each section having a plurality of memory units and each memory unit having a unique corresponding address, the corresponding address using the binary system, the control circuit comprising:
- an access module for receiving the given address;
- a sorting module for making the corresponding address of the section with greater size smaller than the corresponding address of the section with smaller size, and if the size of a first section is equal to the size of a second section, the first and the second sections are capable of being swapped;
- and
- a comparing module for building a bit-pattern for each section based on its corresponding addresses and sending a plurality of comparison signals after comparing the given address with those of each bit-pattern.
Dependencies are inferred from the claim text.