Technique for incorporating power information in register transfer logic design
AssigneeSun Microsystems, Inc.
InventorsAninda Roy, Vipul Parikh
Life of this patent
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Abstract
A technique for incorporating power information in a register transfer level design involves defining a module representing an integrated circuit block having its own power grid. The integrated circuit block, when in a power off mode effectuated by a deactivation of a clock signal to the integrated circuit, uses a device dependent on a power grid of an adjoining integrated circuit block to preserve output information from the integrated circuit block to the adjoining integrated circuit block.
Claims12
A method for register transfer level design, comprising:
- modeling a first portion of an integrated circuit design having a first power grid, wherein the first portion is arranged to receive a clock signal, wherein the first portion goes to a power-off mode when the clock signal to the first portion is deactivated, wherein the first portion comprises a device arranged to output to a second portion of the integrated circuit design having a second power grid, and wherein the device is dependent on the second power grid;
- defining a module representing the first portion as having a clock power domain, wherein the clock power domain is dependent on whether the first portion is in the power-off mode;
- and
- defining the module as having a logic power domain, wherein the logic power domain is dependent on whether the first portion is in the power-off mode.
A computer-readable medium having instructions recorded thereon, the instructions for:
- modeling an integrated circuit block as a register transfer level design module;
- defining a clock power domain for the register transfer level design module, wherein the clock power domain is dependent on power consumption of the integrated circuit block related to a clock signal input to the integrated circuit block;
- and
- defining a logic power domain for the register transfer level design module, wherein the logic power domain is dependent on power consumption of the integrated circuit block related to at least one state device in the integrated circuit block.
A computer system for generating a register transfer level design of an integrated circuit, comprising:
- a processor;
- a memory;
- and
- instructions residing in the memory and executable in the processor, the instructions for:
- modeling a section of the integrated circuit as a register transfer level design module;
- defining a clock power domain for the register transfer level design module, wherein the clock power domain is dependent on power consumption of the section related to a clock signal input to the section;
- and
- defining a logic power domain for the register transfer level design module, wherein the logic power domain is dependent on power consumption of the section related to at least one state device in the section.
Dependencies are inferred from the claim text.