Power allocation in a communication system
OwnerOlav Tirkkonen, Pirjo Pasaneninventors
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Abstract
A communication system, in which bit loading and power allocation are addressed, transfers data between a transmitter and a receiver over a plurality of channels. The system comprises modulation circuitry having a plurality of different modulation alphabets thereby providing a set of possible bit loading sequences. The system also has circuitry for determining the power to be allocated for each bit loading sequence based on minimizing the error rate and circuitry for selecting the bit loading sequence with the lowest error rate.
Claims23
A communication system for transferring data between a transmitter and a receiver over a plurality of channels, the communication system comprising:
- modulation circuitry having a plurality of modulation alphabets providing a set of bit loading sequences;
- circuitry for determining a power allocation for at least one bit loading sequence based on minimizing an error rate;
- and
- circuitry for selecting a bit loading sequence with a lowest error rate.
A method for transferring data between a transmitter and receiver over a communication channel, the method comprising:
- identifying a set of bit loading sequences from a plurality of modulation alphabets;
- determining a power allocation for at least one bit loading sequence based on minimizing an error rate;
- and
- selecting a bit loading sequence with a lowest error rate and applying the power allocation to at least one communication channel.
A communication system for transferring data between a transmitter and receiver over a communication channel, the system comprising:
- a first circuitry means for decomposing a communication channel into a plurality of logical channels;
- modulation circuitry having a plurality of modulation alphabets, at least two modulation alphabets are capable of representing data using a different number of bits so that for a fixed data rate a set of bit loading sequences is identified which specify a number of bits to be loaded onto corresponding logical channels;
- a second circuitry means for allocating a power weighting to the corresponding logical channels for minimizing a bit error rate of the identified bit loading sequences;
- and
- a third circuitry for choosing a bit loading sequence having a minimum bit error rate.
A method for transferring data between a transmitter and receiver over a communication channel, the method comprising:
- decomposing a communication channel into a plurality of logical channels;
- selecting from a plurality of modulation alphabets, wherein at least two modulation alphabets for modulating data are capable of representing the data using a different number of bits;
- identifying a set of bit loading sequences for a fixed data rate which specify a number of bits to be loaded onto corresponding logical channels of the plurality of channels;
- allocating a power weighting to the corresponding logical channel for minimizing a bit error rate of corresponding bit loading sequences from the set of bit loading sequences;
- and
- choosing a bit loading sequence having a minimum bit error rate.
A communication system for transferring data between a transmitter and receiver over a communication channel, the system comprising:
- decomposing means for decomposing a communication channel into a plurality of logical channels;
- representing means for representing data using a different number of bits so that for a fixed data rate a set of bit loading sequences is identified which specify a number of bits to be loaded onto corresponding logical channels;
- allocating means for allocating a power weighting to the corresponding logical channels for minimizing a bit error rate of the identified bit loading sequences;
- and
- choosing means for choosing a bit loading sequence having a minimum bit error rate.
A communication system for transferring data between a transmitter and a receiver over a plurality of channels, the communication system comprising:
- providing means for providing a modulation circuitry having a plurality of modulation alphabets and for providing a set of bit loading sequences;
- determining means for determining a power allocation for at least one bit loading sequence based on minimizing an error rate;
- and
- selecting means for selecting a bit loading sequence with a lowest error rate.
Dependencies are inferred from the claim text.