Mask layer and interconnect structure for dual damascene semiconductor manufacturing
OwnerIsaiah O. Oladeji, Scott Jessen +1inventors
InventorsIsaiah O. Oladeji, Scott Jessen, Joseph Ashley Taylor
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Abstract
A novel mask layer is used in the dual damascene construction of an interconnect structure of an integrated circuit device. The interconnect structure has a low-k dielectric material. The mask layer has a passivation film deposited on the low-k dielectric material, a barrier film is deposited over the passivation film and a metallic film is deposited over the barrier film. The metallic film increases the overall etch selectivity of the mask layer to assure a faithful transfer of via and trench features to the low-k dielectric material during the etching steps of the dual damascene process.
Claims20
A mask layer overlaying a low k dielectric material deposited over an underlying metal layer of an integrated circuit device, for use in the construction of an interconnect structure of the integrated circuit device, said mask layer comprising:
- (a) a passivation mask film deposited on the low-k dielectric material;
- (b) a barrier mask film deposited over the passivaton mask film;
- and,
- (c) a metallic mask film deposited over the barrier mask film.
A method of forming a dual damascene interconnect structure of an integrated circuit device, said interconnect structure having a low-k dielectric material deposited over an underlying metal layer, comprising the steps of:
- (a) forming a passivation mask film over the low-k dielectric material;
- (b) forming a barrier mask film over the passivation mask film;
- (c) forming a metallic mask film over the barrier mask film, and said passivation barrier and metallic mask films forming a mask layer overlaying said low-k dielectric material;
- (d) etching a trench within the low-k dielectric material to a predetermined depth of the low-k dielectric material;
- and,
- (e) etching a via through the low-k dielectric material to the underlying metal layer.
The method of claim 8 wherein said barrier mask film comprises silicon nitride.
The method of forming an interconnect structure on an integrated circuit device having a low-k dielectric material deposited over an underlying metal layer, and a mask layer deposited on the low-k dielectric material, and said mask layer having a desired etch selectivity with respect to the low-k dielectric material, the method comprising the step of forming a metallic film as part of the mask layer to increase the etch selectivity of the mask layer with respect to the low-k dielectric layer.
Dependencies are inferred from the claim text.