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US 2004/0171252 A1Published application
Reduced contamination of tools in semiconductor processing
OwnerHaoren Zhuang, Katsuaki Natori +5inventors
InventorsHaoren Zhuang, Katsuaki Natori, Gerhard Beitel, Bum-ki Moon, Moto Yabuki, Yoshitaka Tsunashima, Karl Hornik
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Abstract
An improved method of reducing contamination in processing of ICs is disclosed. The method includes forming a contamination protection layer on at least the back surface of the substrate. The contamination protection layer comprises a low diffusion factor and can be cleaned efficiently. In one embodiment, the contamination protection layer comprises HCD silicon nitride.
Claims24
In manufacturing of integrated circuits (ics) a method of reducing contamination comprising:
- providing a substrate having top, bottom and side surfaces;
- and
- forming a contamination protection layer on at least the bottom surface of the substrate, the contamination protection layer having a low diffusion factor which can be cleaned efficiently.
Dependencies are inferred from the claim text.