Prevention of post CMP defects in CU/FSG process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Shi Liu, Shau-Lin Shue
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Abstract
A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any fluorine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.
Claims22
A process for filling a via hole in a layer of FSG, having an upper surface, comprising the sequential steps of:
- depositing the layer of FSG on a substrate;
- depositing a layer of USG on the upper surface;
- patterning and then etching said USG and FSG layers, whereby a via hole, having walls and extending as far as the substrate, is formed;
- depositing a seed layer on the walls of the via hole;
- overfilling the via hole with a material;
- and
- by means of CMP, removing said material until said USG layer is reached.
A process for forming a single damascene connector, comprising the sequential steps of:
- providing a partially completed integrated circuit and then depositing thereon a layer of FSG having an upper surface;
- depositing a layer of USG on said upper surface;
- on the USG layer, depositing a layer of silicon oxynitride for use as an anti-reflection coating;
- patterning and then etching said oxynitride, USG, and FSG layers, thereby forming a via hole extending as far as said integrated circuit;
- depositing a barrier layer on all walls of the via hole;
- depositing a copper seed layer on said barrier layer;
- overfilling the via hole with copper;
- and
- by means of CMP, removing the copper until said USG layer is reached, thereby forming said damascene connector.
A process for forming a dual damascene connector, comprising the sequential steps of:
- providing a partially completed integrated circuit and then depositing thereon a layer of silicon nitride;
- on said layer of silicon nitride, depositing a layer of FSG having an upper surface;
- depositing a layer of USG on said upper surface;
- on the USG layer, depositing a layer of silicon oxynitride for use as an anti-reflection coating;
- patterning and then etching said oxynitride, USG, and FSG layers, thereby forming a trench in said upper surface;
- patterning and then etching said FSG layer, including said trench, whereby a via hole extending as far as said layer of silicon nitride is formed inside said trench;
- selectively removing the layer of silicon nitride;
- depositing a barrier layer on all walls of said trench and said via hole;
- depositing a copper seed layer on said barrier layer;
- overfilling said via hole and said trench with copper;
- and
- by means of CMP, removing the copper until said USG layer is reached, thereby forming said damascene connector.
A filled via hole in a layer of FSG, comprising:
- said layer of FSG being on a substrate;
- a layer of USG, having an upper surface, on the layer of FSG;
- said via hole extending from said upper surface to the substrate;
- and
- the via hole being filled with a material.
A single damascene connector, comprising:
- a layer of FSG on a partially completed integrated circuit having a surface;
- a layer of USG, having a first upper surface, on said layer of FSG;
- a via hole extending from said first upper surface as far as the surface of the integrated circuit;
- a barrier layer on all walls of the via hole;
- and
- the via hole being filled with copper having a second upper surface that is flush with said first upper surface.
A dual damascene connector, comprising:
- a layer of FSG on a partially completed integrated circuit having a surface;
- a layer of USG, having a first upper surface, on said layer of FSG;
- a trench, extending from said first upper surface through the USG layer a distance into the FSG layer, said trench having first sidewalls and a floor;
- a via hole, having second sidewalls, extending from said trench floor through the FSG layer, as far as the surface of the integrated circuit;
- a barrier layer on the first and second sidewalls and on the trench floor;
- and
- the via hole and trench being filled with copper that has a second upper surface that is flush with said first upper surface.
Dependencies are inferred from the claim text.