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US 2004/0171247 A1Published application
Methods for making semiconductor structures having high-speed areas and high-density areas
AssigneeMicron Technology, Inc.
InventorsChih-Chen Cho, Zhongze Wang
Life of this patent
Estimating the term…
Abstract
Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a metallization layer simultaneously into the high-density area and the high-speed area. The metallization layer includes a combination of substances and compounds that reduce vertical resistance, reduce horizontal resistance, and inhibit cross-diffusion.
Claims49
A method for making a semiconductor structure in a substrate having an array area and a periphery area, the method comprising:
- forming a transistor in the array area and a transistor in the periphery area;
- forming a stopping layer over the transistors in the array area and the periphery area, the stopping layer having a characteristic to stop an etching process when consumed by the etching process;
- forming over the stopping layer a nonconductive layer;
- forming openings by etching the nonconductive layer and the stopping layer;
- and
- forming a metallization layer by filling the openings with conductive substances and compounds, the metallization layer forming a local interconnect layer for the transistor in the array area and forming a strapping layer for the transistor in the periphery area.
3 more elements
A method for making a semiconductor structure in a semiconductor substrate having an array and a periphery, the method comprising:
- depositing a nonconductive stack over a gate and source/drain of a memory cell in the array and over a gate of a transistor in the periphery, the nonconductive stack including a stopping layer and a nonconductive layer;
- photolithographing to mark portions of the array and the periphery, the portions of the array including portions that are superjacent to the gate and source/drain of the memory cell in the array, the portions of the periphery includes portions that are superjacent to the gate of the transistor;
- removing the portions of the array and the periphery that are marked to expose the gate and source/drain of the memory cell in the array and to expose the gate of the transistor in the periphery;
- and
- depositing simultaneously local interconnect materials into portions of the array and the periphery that were removed by the act of removing.
2 more elements
A method for making a semiconductor structure in a substrate having an array and a periphery, comprising:
- photolithographing to mask portions of gates in the array and the periphery;
- dry-etching portions of the gates that are masked;
- depositing over the gates a nonconductive stack having a stopping layer;
- photolithographing portions of the array and the periphery that include the gates;
- dry-etching the portions of the array and the periphery until stopped by the stopping layer;
- and
- depositing simultaneously local interconnect materials into portions of the array and the periphery that are etched by the act of dry-etching.
4 more elements
A circuitry module, comprising:
- a plurality of dies, wherein at least one die includes a memory device;
- a plurality of leads coupled to the plurality of dies to provide unilateral or bilateral communication and control, wherein the memory device includes a transistor in a periphery that is made from a method that includes:
- forming from a nonconductive stack a trench that superjacently abuts along a substantial length of a dual-doped polycrystalline silicon line having a p-type strip adjoining an n-type strip, the nonconductive stack including a stopping layer that stops an etching process once etched away to define the bottom of the trench;
- and
- filling the trench with a conductive stack to strap the dual-doped polycrystalline silicon line, the trench having a large cross-sectional area to decrease a horizontal resistance of the semiconductor device so as to increase the performance of the semiconductor device in the periphery.
2 more elements
A memory module, comprising:
- a plurality of memory devices;
- a plurality of command links coupled to the plurality of memory devices to communicate at least one command signal;
- a plurality of data links coupled to the plurality of memory devices to communicate data, wherein at least one memory device of the plurality of memory devices includes a transistor in a periphery that is made from a method that includes:
- forming from a nonconductive stack a trench that superjacently abuts along a substantial length of a dual-doped polycrystalline silicon line having a p-type strip adjoining an n-type strip, the nonconductive stack including a stopping layer that stops an etching process once etched away to define the bottom of the trench;
- and
- filling the trench with a conductive stack to strap the dual-doped polycrystalline silicon line, the trench having a large cross-sectional area to decrease a horizontal resistance of the semiconductor device so as to increase the performance of the semiconductor device in the periphery.
3 more elements
An electronic system, comprising:
- a plurality of circuit modules that includes a plurality of dies, wherein at least one die includes at least one memory device;
- a plurality of leads coupled to the plurality of dies to provide unilateral or bilateral communication and control;
- a user interface, wherein the at least one memory device includes a transistor in a periphery that is made from a method that includes:
- forming from a nonconductive stack a trench that superjacently abuts along a substantial length of a dual-doped polycrystalline silicon line having a p-type strip adjoining an n-type strip, the nonconductive stack including a stopping layer that stops an etching process once etched away to define the bottom of the trench;
- and
- filling the trench with a conductive stack to strap the dual-doped polycrystalline silicon line, the trench having a large cross-sectional area to decrease a horizontal resistance of the semiconductor device so as to increase the performance of the semiconductor device in the periphery.
3 more elements
A memory system, comprising:
- a plurality of memory modules that includes a plurality of memory devices;
- a plurality of command links coupled to the plurality of memory devices to communicate at least one command signal;
- a plurality of data links coupled to the plurality of memory devices to communicate data;
- a memory controller, wherein one of the memory device includes a transistor in a periphery that is made from a method that includes:
- forming from a nonconductive stack a trench that superjacently abuts along a substantial length of a dual-doped polycrystalline silicon line having a p-type strip adjoining an n-type strip, the nonconductive stack including a stopping layer that stops an etching process once etched away to define the bottom of the trench;
- and
- filling the trench with a conductive stack to strap the dual-doped polycrystalline silicon line, the trench having a large cross-sectional area to decrease a horizontal resistance of the semiconductor device so as to increase the performance of the semiconductor device in the periphery.
4 more elements
A computer system, comprising:
- a processor;
- a memory system that comprises a plurality of memory modules, one of the plurality of the memory modules comprises a plurality of memory devices;
- a plurality of command links coupled to the plurality of memory devices to communicate at least one command signal;
- a plurality of data links coupled to the plurality of memory devices to communicate data;
- a memory controller;
- at least one user interface device, wherein the at least one user interface device includes a monitor;
- at least one output device, wherein the at least one output device includes a printer;
- at least one bulk storage device, wherein at least one memory device of the plurality of memory devices includes a transistor in a periphery that is made from a method that includes:
- forming from a nonconductive stack a trench that superjacently abuts along a substantial length of a dual-doped polycrystalline silicon line having a p-type strip adjoining an n-type strip, the nonconductive stack including a stopping layer that stops an etching process once etched away to define the bottom of the trench;
- and
- filling the trench with a conductive stack to strap the dual-doped polycrystalline silicon line, the trench having a large cross-sectional area to decrease a horizontal resistance of the semiconductor device so as to increase the performance of the semiconductor device in the periphery.
8 more elements
A method for strapping a gate structure in a periphery of a semiconductor device, the gate structure includes a polycrystalline silicon layer having a p-type strip abutting an n-type strip, the p-type strip and the n-type strip defining a length of the polycrystalline silicon layer, the method comprising:
- exposing the polycrystalline silicon layer substantially along the length;
- forming over the polycrystalline silicon layer a nonconductive stack that includes a stopping layer and a nonconductive layer, the stopping layer having a characteristic to stop an etching process once consumed by the etching process;
- etching the nonconductive stack to expose the polycrystalline silicon layer substantially along the length to form a trench;
- and
- filling the trench with a conductive stack having a silicide layer to reduce the vertical resistance of the gate structure and a conductive layer to reduce the horizontal resistance of the gate structure.
2 more elements
A method for making a semiconductor structure in a periphery, the method comprising:
- forming a single polycrystalline line having a p-type strip adjoining an n-type strip;
- forming a stopping layer over the single polycrystalline line, forming a nonconductive layer over the stopping layer;
- forming a trench having a depth defined by etching the nonconductive layer until the act of etching stops when the stopping layer is etched away;
- and
- filling the trench with a conductive stack that includes titantium, titanium nitride, and tungsten to reduce vertical resistance and horizontal resistance.
2 more elements
A method for strapping a semiconductor device in a periphery, comprising:
- forming from a nonconductive stack a trench that superjacently abuts along a substantial length of a dual-doped polycrystalline silicon line having a p-type strip adjoining an n-type strip, the nonconductive stack including a stopping layer that stops an etching process once etched away to define the bottom of the trench;
- and
- filling the trench with a conductive stack to strap the dual-doped polycrystalline silicon line, the trench having a large cross-sectional area to decrease a horizontal resistance of the semiconductor device so as to increase the performance of the semiconductor device in the periphery.
A method for forming a routing in a periphery area of a semiconductor structure, comprising:
- forming from a nonconductive stack a trench that superjacently abuts along a substantial length of a gate stack in the periphery, the nonconductive stack including a stopping layer that stops an etching process once etched away to define the bottom of the trench;
- and
- filling the trench with a conductive stack to form the routing over the gate stack, the trench having a large cross-sectional area to decrease a horizontal resistance of the routing.
A method for forming a contact to an active region in a periphery of a semiconductor structure, comprising:
- forming from a nonconductive stack an opening that abuts an active region in the periphery, the nonconductive stack including a stopping layer that stops an etching process once etched away to define the bottom of the trench;
- and
- filling the opening with a conductive stack to form a contact over the gate stack, the trench having a predetermined cross-sectional area to decrease a horizontal resistance of the contact.
A method for making semiconductor structures on a substrate having an array area and a periphery area, comprising:
- forming from a nonconductive stack a number of openings to expose a number of semiconductor structures in the array area and in the periphery area, the nonconductive stack including a stopping layer to stop an etching process once etched away to define the bottom of each opening;
- and
- filling the number of openings with a conductive stack having the characteristic to reduce a vertical resistance of each semiconductor structure and a horizontal resistance of each semiconductor structure so as to increase the performance of each semiconductor structure.
Dependencies are inferred from the claim text.