Reduced mask count buried layer process
AssigneeIntersil Americas Inc.
InventorJames D. Beasom
Life of this patent
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Abstract
An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of the P type buried layer dopant is greater than the N type buried layer dopant so that connections can be made to the P type buried layer by P wells which have a lower dopant concentration than the N buried layer.
Claims56
A method of fabricating a semiconductor device comprising the steps of:
- a) forming a non selective N type buried layer comprising a first majority dopant having a first coefficient of diffusion;
- and
- b) forming a selective P type buried layer comprising a second majority dopant having a coefficient of diffusion greater than said first coefficient of diffusion.
A method of fabricating a semiconductor device in a wafer comprising the steps of:
- a) implanting across all of said wafer an N type dopant having a first coefficient of diffusion and at a first dose level;
- b) diffusing said N type dopant into said wafer to form an N type buried layer;
- c) masking a portion of said wafer;
- d) implanting into said wafer in areas not masked a P type dopant having a coefficient of diffusion greater than said first coefficient of diffusion;
- and
- e) diffusing said p type dopants into said wafer to form a P type buried layer.
A method of fabricating a semiconductor device in a wafer comprising the steps of:
- a) growing an epitaxial layer doped with an n type dopant having a first coefficient of diffusion and a first doping level to form an N type buried layer;
- b) masking a portion of said wafer;
- c) implanting into said wafer in areas not masked a P type dopant having a coefficient of diffusion greater than said first coefficient of diffusion;
- and
- d) diffusing said p type dopants into said wafer to form a P type buried layer.
A method of fabricating a semiconductor device in a wafer comprising the steps of:
- a) bonding a device wafer doped N type to a first doping level with a dopant having a first coefficient of diffusion to a handle wafer by insulator bonding and separating a desired thickness of said device wafer to form an SOI layer which is also an N type buried layer;
- b) introducing P type dopants having a second coefficient of diffusion greater than said first coefficient of diffusion in a selected region of said SOI layer to form a P type buried layer;
- c) forming an epitaxial layer on the surface of said SOI layer;
- and
- d) diffusing so that the P type dopants extend up into said epitaxial layer further than the N type dopants in said SOI layer.
A method for forming an N++buried layer comprising the steps of:
- a) oxidizing the top and bottom surfaces of an N+ device wafer;
- b) bonding a handle wafer to said bottom oxide layer;
- and
- c) removing said top oxide layer.
A method for forming an N+ buried layer comprising the steps of:
- a) providing a device wafer bonded to an oxide layer which, in turn, is bonded to a handle wafer;
- b) implanting N type dopants into said device wafer across the entire top surface of said device wafer;
- and
- c) diffusing said N type dopants into said device wafer.
Dependencies are inferred from the claim text.